An Qi Zhang, Andrés Goens, Nicolai Oswald, Tobias Grosser, Daniel J. Sorin, and Vijay Nagarajan. “PipeGen: Automated Transformation of a Single-Core Pipeline into a Multicore Pipeline for a Given Memory Consistency Model.” International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2024.
Weihang Li, Nicolai Oswald, Andrés Goens, Vijay Nagarajan, and Daniel J. Sorin. “Determining the Minimum Number of Virtual Networks for Different Coherence Protocols.” 51st International Symposium on Computer Architecture (ISCA), June 2024.
Beyza Dabak, Major Glenn, Jingyang Liu, Alexander Buck, Siyi Yang, Robert Calderbank, Natalie Enright Jerger, and Daniel J. Sorin. “Low-Energy Line Codes for On-Chip Networks.” arXiv 2405.14783, May 2024.
An Qi Zhang, Andrés Goens, Nicolai Oswald, Tobias Grosser, Daniel J. Sorin, and Vijay Nagarajan. “PipeGen: Automatically Transforming a Single-Core Pipeline into a Multi-core Pipeline Enforcing a Given Memory Model.” 4th Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), April 2024.
Daniel
Sorin. "Optimizing
Multi-Robot Workcell Performance." Motion Design, October
2023.
Filip Mazurek, Arya Tschand, Yu Wang, Miroslav Pajic, and Daniel J.
Sorin. "Rigorous
Evaluation of Computer Processors with Statistical Model Checking."
56th IEEE/ACM International Symposium on Microarchitecture (MICRO), October
2023.
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis Gavrielatos, Theo Olausson, and Reece Carr. “HeteroGen: Automatic Synthesis of Heterogeneous Cache Coherence Protocols.” IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, vol 43, issue 4, July/August 2023.
Vijay Nagarajan, Daniel J. Sorin, and Nicolai Oswald. “Insights from *Gen: Correct-by-construction Cache Coherence Protocols.” 3rd Workshop on Languages, Tools, and Techniques for Accelerator Design (LATTE), March 2023.
Atefeh Mehrabi, Daniel J. Sorin, and Benjamin C. Lee. "Spatiotemporal FPGA Scheduling for Long-term FPGA Resource Management." IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), May 2022.
Nicolai Oswald, Vijay Nagarajan, Daniel J. Sorin, Vasilis
Gavrielatos, Theo Olausson, and Reece Carr. “HeteroGen:
Automatic Synthesis of Heterogeneous Cache Coherence Protocols.”
28th IEEE International Symposium on High-Performance Computer Architecture
(HPCA-28), April 2022. Selected as IEEE Micro Top Pick.
Atefeh Mehrabi, Donghyuk Lee, Niladrish Chatterjee, Daniel J. Sorin, Benjamin C. Lee, and Mike O’Connor. “Learning Sparse Matrix Row Permutations for Efficient SpMM on GPU Architectures.” IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2021.
Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, and Daniel J. Sorin. “Bayesian Optimization for Efficient Accelerator Synthesis.” ACM Transactions on Architecture and Code Optimization (TACO), volume 18, issue 1, 2021.
Sean Murray, George Konidaris, and Daniel J. Sorin. “Roadmap Subsampling for Changing Environments.” IEEE/RSJ International Conference on Intelligent Robots and Systems (IROS), October 2020.
Benchmark generation kit: download
Nicolai Oswald, Vijay Nagarajan, and Daniel J. Sorin. “HieraGen: Automatically Generating Hierarchical Cache Coherence Protocols from Atomic Specifications.” 47th International Symposium on Computer Architecture (ISCA), June 2020.
Samantha Archer, Georgios Mappouras, Daniel J. Sorin, and Robert Calderbank. “Foosball Coding: Correcting Shift Errors and Bit Flip Errors in 3D Racetrack Memory.” 50th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019), June 2020.
Atefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, and Daniel J. Sorin. “Prospector: Synthesizing Efficient Accelerators via Statistical Learning.” Design, Automation & Test in Europe (DATE), March 2020.
Vijay Nagarajan, Daniel J. Sorin, Mark D. Hill, and David A. Wood. "A Primer on Memory Consistency and Cache Coherence," 2nd edition, Synthesis Lectures in Computer Architecture, Morgan & Claypool Publishers, February 2020. OPEN ACCESS
Sean Murray, Will Floyd-Jones, George Konidaris, and Daniel J. Sorin. “A Programmable Architecture for Robot Motion Planning Acceleration.” 30th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP 2019), July 2019.
Georgios Mappouras, Alireza Vahid, Robert Calderbank, and Daniel J. Sorin. “GreenFlag: Protecting 3D-Racetrack Memory from Shift Errors.” 49th IEEE/IFIP International Conference on Dependable Systems and Networks (DSN 2019), June 2019. One of three finalists for Best Paper Award.
Nicolai Oswald, Vijay Nagarajan, and Daniel J. Sorin. “ProtoGen: Automatically Generating Directory Cache Coherence Protocols from Atomic Specifications.” 45th International Symposium on Computer Architecture (ISCA), June 2018. Honorable Mention from IEEE Micro's annual Top Picks in Computer Architecture.
Georgios Mappouras, Alireza Vahid, Robert Calderbank, Derek R. Hower, and Daniel J. Sorin. "Jenga: Efficient Fault Tolerance for Stacked DRAM." 35th IEEE International Conference on Computer Design (ICCD), November 2017.
Opeoluwa Matthews and Daniel J. Sorin. "Architecting Hierarchical Coherence Protocols for Push-Button Parametric Verification." 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2017.
Sean Murray, Will Floyd-Jones, Ying Qi, Daniel Sorin, and George Konidaris. "The Microarchitecture of a Real-Time Robot Motion Planning Accelerator." 49th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), October 2016.
Opeoluwa Matthews, Jesse D. Bingham, and Daniel J. Sorin. "Verifiable Hierarchical Protocols with Network Invariants on Parametric Systems." Formal Methods in Computer-Aided Design (FMCAD), October 2016.
Sean Murray, Will Floyd-Jones, Ying Qi, Daniel Sorin, and George Konidaris. "Robot Motion Planning on a Chip." Robotics: Science and Systems (RSS), June 2016. (accompanying video)
Georgios Mappouras, Alireza Vahid, Robert Calderbank, and Daniel J. Sorin. "Methuselah Flash: Rewriting Codes for Extra-Long Storage Lifetime." 46th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN), June 2016.
Ralph Nathan, Helia Naeimi, Daniel J. Sorin, and Xiaobai Sun. "Profile-Driven Automated Mixed Precision." arXiv, June 2016.
Helia Naeimi, Ralph Nathan, Daniel J. Sorin, Shih-Lien L. Lu. "Recycling Error Bits in Floating Point Units." United States Patent 9,335,996, issued May 2016.
Yaqi Zhang, Ralph Nathan, and Daniel J. Sorin. "Reduced Precision Checking to Detect Errors in Floating Point Arithmetic." Silicon Errors in Logic - System Effects (SELSE), March 2016.
Blake A. Hechtman, Andrew D. Hilton, and Daniel J. Sorin. "TREES: A CPU/GPU Task-Parallel Runtime with Explicit Epoch Synchronization." arXiv:1608.00571v1, 2016.
Ali Eslami, Alfredo Velasco, Alireza Vahid, Georgios Mappouras, Robert Calderbank, and Daniel J. Sorin. "Writing without Disturb on Phase Change Memories by Integrating Coding and Layout Design." International Symposium on Memory Systems (MEMSYS), October 2015.
Meng Zhang, Jesse D. Bingham, John Erickson, and Daniel J. Sorin. "PVCoherence: Designing Flat Coherence Protocols for Scalable Verification." IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, 2015.
Adam N. Jacobvitz, Andrew D. Hilton, and Daniel J. Sorin. "Multi-Program Benchmark Definition." IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2015.
Ralph Nathan, Bryan Anthonio, Shih-Lien Lu, Helia Naeimi, Daniel J. Sorin, and Xiaobai Sun. "Recycled Error Bits: Energy-Efficient Architectural Support for Floating Point Accuracy." SC '14, November 2014.
Daniel J. Sorin, Opeoluwa Matthews, and Meng Zhang. "Architecting Dynamic Power Management to be Formally Verifiable." Design Automation Conference (DAC), June 2014.
John Ingalls, Adam Jacobvitz, Patrick Eibl, Michael Ansel and Daniel Sorin. "Experiences in Developing and Evaluating a Low-Cost Soft-Error-Tolerant Multicore Processor." 10th Workshop on Silicon Errors in Logic - System Effects (SELSE), April 2014.
Ralph Nathan and Daniel J. Sorin. "Argus-G: Comprehensive, Low-Cost Error Detection for GPGPU Cores." Computer Architecture Letters, volume 14, issue 1, 2014.
Ralph Nathan and Daniel J. Sorin. "Nostradamus: Low-Cost Hardware-Only Error Detection for Processor Cores." Design, Automation & Test in Europe (DATE), March 2014.
Adam N. Jacobvitz, Robert Calderbank, and Daniel J. Sorin. "Coset Coding to Extend the Lifetime of Non-Volatile Memory." Non-Volatile Memories Workshop (NVM-W), March 2014.
Meng Zhang, Jesse D. Bingham, John Erickson, and Daniel J. Sorin. "PVCoherence: Designing Flat Coherence Protocols for Scalable Verification." 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014. Best Paper Award.
Opeoluwa Matthews, Meng Zhang, and Daniel J. Sorin. "Scalably Verifiable Dynamic Power Management." 20th International Symposium on High Performance Computer Architecture (HPCA), February 2014.
2013
Kushal Seetharam, Lance Co Ting Keh, Ralph Nathan, and Daniel J. Sorin. "Applying Reduced Precision Arithmetic to Detect Errors in Floating Point Multiplication." 19th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC), December 2013.
Blake A. Hechtman and Daniel J. Sorin. " Exploring Memory Consistency for Massively-Threaded Throughput-Oriented Processors ." International Symposium on Computer Architecture (ISCA), June 2013.
Blake A. Hechtman and Daniel J. Sorin. "Evaluating Cache Coherent Shared Virtual Memory for Heterogeneous Multicore Chips." Extended abstract and poster in the IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), April 2013. The full paper appears as Duke University Department of ECE Technical Report Duke-ECE-TR-2013-6-5.
Adam N. Jacobvitz, A. Robert Calderbank, and Daniel J. Sorin. "Coset Coding to Improve the Lifetime of Memory." 19th International Symposium on High Performance Computer Architecture (HPCA), February, 2013.
Adam N. Jacobvitz, A. Robert Calderbank, and Daniel J. Sorin. "Writing Cosets of a Convolutional Code to Increase the Lifetime of Flash Memory. 50th Annual Allerton Conference on Communication, Control, and Computing, October, 2012.
Milo M. K. Martin, Mark D. Hill, and Daniel J. Sorin. "Why On-Chip Cache Coherence Is Here to Stay." Communications of the ACM, vol 55, no 7, July 2012.
Blake A. Hechtman and Daniel J. Sorin. "The Limits of Concurrency in Cache Coherence ." 10th Annual Workshop on Duplicating, Deconstructing, and Debunking (WDDD), June 2012.
Milo M. K. Martin, Mark D. Hill, and Daniel J. Sorin. "Why On-Chip Cache Coherence Is Here to Stay." Duke University Department of ECE Technical Report TR-2011-1, August 16 2011.
Patrick J. Eibl, Albert Meixner, and Daniel J. Sorin. "An FPGA-Based Experimental Evaluation of Microprocessor Core Error Detection with Argus-2." SIGMETRICS, June 2011.
Daniel J. Sorin, Mark D. Hill, and David A. Wood. "A Primer on Memory Consistency and Cache Coherence." Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, May 2011.
Dimitris Gizopoulos, Mihalis Psarakis, Sarita V. Adve, Pradeep Ramachandran, Siva Kumar Sastry Hari, Daniel Sorin, Albert Meixner, Arijit Biswas, and Xavier Vera. "Architectures for Online Error Detection and Recovery in Multicore Processors." Design, Automation & Test in Europe (DATE), March 2011.
Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. "Address Translation-Aware Memory Consistency." IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, January/February 2011.
Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin. "Fractal Consistency: Architecting the Memory System to Facilitate Verification." Computer Architecture Letters, volume 9, number 2, July-December 2010.
Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin. "Fractal Coherence: Scalably Verifiable Cache Coherence." 43rd International Symposium on Microarchitecture (MICRO), December 2010.
Ralph Nathan and Daniel J. Sorin. "Argus-G: A Low-Cost Error Detection Scheme for GPGPUs." Workshop on Resilient Architectures (WRA), December 2010.
Bogdan F. Romanescu, Alvin R. Lebeck, and Daniel J. Sorin. "Specifying and Dynamically Verifying Address Translation-Aware Memory Consistency." 15th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), March 2010.
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. Sorin, and Anne Bracy. "UNified Instruction/Translation/Data (UNITD) Coherence: One Protocol to Rule Them All." 16th IEEE International Symposium on High-Performance Computer Architecture, January 2010.
Daniel J. Sorin. "Fault Tolerant Computer Architecture." Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, 2009.
Patrick J. Eibl, Daniel J. Sorin, and Andrew D. Cook. "Reduced Precision Checking for a Floating Point Adder." 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009.
Meng Zhang, Anita Lungu, and Daniel J. Sorin. "Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms." 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, October 2009.
Anita Lungu, Pradip Bose, Alper Buyuktosunoglu and Daniel J. Sorin. "Dynamic Power Gating with Quality Guarantees." International Symposium on Low Power Electronics and Design (ISLPED), August 2009.
Anita Lungu, Pradip Bose, Daniel Sorin, Steven German and Geert Janssen. "Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification." Seventh ACM-IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE), July 2009.
Michael E. Bauer, Albert Meixner, and Daniel J. Sorin. "Proving the Completeness of the Composition of Two Dynamic Verification Techniques." Technical Report Duke-ECE-2009-1, May 2009.
Albert Meixner and Daniel J. Sorin. "Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures." IEEE Transactions on Dependable and Secure Computing (TDSC), volume 6, number 1, January-March 2009.
Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, and Geert Janssen. "Multicore Power Management: Ensuring Robustness via Early-Stage Formal Verification." 3rd Workshop on Dependable Architectures (WDA-3), November 2008.
Bogdan F. Romanescu and Daniel J. Sorin. "Core Cannibalization Architecture: Improving Lifetime Chip Performance for Multicore Processors in the Presence of Hard Faults." Seventeenth International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2008.
Fred A. Bower, Sule Ozev, Paul G. Shealy, and Daniel J. Sorin. "Self-Repairing of Microprocessor Array Structures." United States Patent 7,415,644, issued August 19, 2008.
Albert Meixner and Daniel J. Sorin. "Detouring: Translating Software to Circumvent Hard Faults in Simple Cores." 38th Annual International Conference on Dependable Systems and Networks (DSN), June 2008.
Albert Meixner and Daniel J. Sorin. "IOTA: Detecting Erroneous I/O Behavior via I/O Transaction Auditing." First Workshop on Compiler and Architectural Techniques for Application Reliability and Security (CATARS), June 2008.
Fred A. Bower, Daniel J. Sorin, and Landon P. Cox. "The Impact of Dynamically Heterogeneous Multicore Processors on Thread Scheduling." IEEE Micro, May/June 2008.
Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. "Reducing the Impact of Intra-Core Process Variability with Criticality-Based Resource Allocation and Prefetching." ACM International Conference on Computing Frontiers, May 2008.
Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores." IEEE Micro: Micro's Top Picks from Computer Architecture Conferences, January/February 2008.
Albert Meixner, Michael E. Bauer, and Daniel J. Sorin. "Argus: Low-Cost, Comprehensive Error Detection in Simple Cores." 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), December, 2007.
Bogdan F. Romanescu, Michael E. Bauer, Sule Ozev, and Daniel J. Sorin. "VariaSim: Simulating Circuits and Systems in the Presence of Process Variability." Computer Architecture News, volume 35, number 5, December 2007.
Mahmut Yilmaz, Sule Ozev, and Daniel J. Sorin. "Low-Cost Run-time Diagnosis of Hard Delay Faults in the Functional Units of a Microprocessor." IEEE International Conference on Computer Design (ICCD), October 2007.
Mahmut Yilmaz, Albert Meixner, Sule Ozev, and Daniel J. Sorin. "Lazy Error Detection for Microprocessor Functional Units." IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS), September 2007.
Anita Lungu and Daniel J. Sorin. "Verification-Aware Microprocessor Design." Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Albert Meixner and Daniel J. Sorin. "Error Detection Using Dynamic Dataflow Verification." Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. "Reducing the Impact of Process Variability with Prefetching and Criticality-Based Resource Allocation." Poster and extended abstract in Sixteenth International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2007.
Fred A. Bower, Daniel J. Sorin, and Sule Ozev. "Online Diagnosis of Hard Faults in Microprocessors." ACM Transactions on Architecture and Code Optimization (TACO), volume 4, number 2, June 2007.
Bogdan F. Romanescu, Michael E. Bauer, Daniel J. Sorin, and Sule Ozev. "A Case for Computer Architecture Performance Metrics that Reflect Process Variability." Duke University, Dept of Electrical and Computer Engineering, Technical Report #2007-2, May 2007.
Albert Meixner and Daniel J. Sorin. "Unified Microprocessor Core Storage." ACM Conference on Computing Frontiers, May 2007.
Albert Meixner and Daniel J. Sorin. "Error Detection via Online Checking of Cache Coherence with Token Coherence Signatures." 13th International Symposium on High-Performance Computer Architecture (HPCA), February 2007.
Bogdan F. Romanescu, Sule Ozev, and Daniel J. Sorin. "Quantifying the Impact of Process Variability on Microprocessor Behavior." 2nd Workshop on Architectural Reliability (WAR), December 2006.
Mahmut Yilmaz, Derek R. Hower, Sule Ozev, and Daniel J. Sorin. "Self-Detecting and Self-Diagnosing 32-bit Microprocessor Multiplier." International Test Conference (ITC), October 2006.
Nathan N. Sadler and Daniel J. Sorin. "Choosing an Error Protection Scheme for a Microprocessor's L1 Data Cache." International Conference on Computer Design (ICCD), October 2006.
Albert Meixner and Daniel J. Sorin. "Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures." International Conference on Dependable Systems and Networks (DSN), June 2006.
Albert Meixner and Daniel J. Sorin. "Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures." Duke University, Dept of Electrical and Computer Engineering, Technical Report #2006-1, April 18, 2006.
Fred A. Bower, Derek H. Hower, Mahmut Yilmaz, Daniel J. Sorin, and Sule Ozev. "Applying Architectural Vulnerability Analysis to Hard Faults in the Microprocessor." Poster and 2-page paper in ACM SIGMETRICS, June 2006.
Tong Li, Alvin R. Lebeck, and Daniel J. Sorin. "Spin Detection Hardware for Improved Management of Multithreaded Systems." IEEE Transactions on Parallel and Distributed Systems (TPDS), volume 17, number 6, June 2006.
Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. "NANA: A Nano-scale Active Network Architecture." ACM Journal on Emerging Technologies in Computing Systems (JETC), volume 2, number 1, January 2006.
Fred A. Bower, Sule Ozev, and Daniel J. Sorin. "Autonomic Microprocessor Execution via Self-Repairing Arrays." IEEE Transactions on Dependable and Secure Computing (TDSC), volume 2, number 4, October-December 2005.
Fred A. Bower, Daniel J. Sorin, and Sule Ozev. "A Mechanism for Online Diagnosis of Hard Faults in Microprocessors." 38th Annual International Symposium on Microarchitecture (MICRO), November 2005.
Milo M.K. Martin, Daniel J. Sorin, Bradford M. Beckmann, Michael R. Marty, Min Xu, Alaa R. Alameldeen, Kevin E. Moore, Mark D. Hill, and David A. Wood. "Multifacet's General Execution-driven Multiprocessor Simulator (GEMS) Toolset." Computer Architecture News (CAN), volume 33, number 4, November 2005.
Albert Meixner and Daniel J. Sorin. "Dynamic Verification of Sequential Consistency." 32nd Annual International Symposium on Computer Architecture (ISCA), June 2005.
Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, Daniel J. Sorin. "Evaluating the Connectivity of Self-Assembled Networks of Nano-scale Processing Elements." IEEE International Workshop on Design and Test of Defect-Tolerant Nanoscale Architectures (NANOARCH '05), May 2005.
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. "Bandwidth-adaptive, Hybrid, Cache-coherence Protocol." United States Patent 6,883,070, issued April 19, 2005.
Tong Li, Carla S. Ellis, Alvin R. Lebeck, and Daniel J. Sorin. "Pulse: A Dynamic Deadlock Detection Mechanism Using Speculative Execution." USENIX Annual Technical Conference, April 2005.
Jonathan R. Carter, Sule Ozev, and Daniel J. Sorin. "Circuit-Level Modeling for Concurrent Testing of Operational Defects due to Gate Oxide Breakdown." Design, Automation, and Test in Europe (DATE), March 2005.
Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. "Self-Assembled Architectures and the Temporal Aspects of Computing." IEEE Computer, volume 38, number 1, January 2005.
Albert Meixner and Daniel J. Sorin. "Clouseau: Probabilistic Dynamic Verification of Multithreaded Memory Systems." Duke University Department of ECE Technical Report #2004-2, September 20, 2004.
Chris Dwyer, Vijeta Johri, Jaidev P. Patwardhan, Alvin R. Lebeck, and Daniel J. Sorin. "Design Tools for Self-assembling Nanoscale Technology." Institute of Physics Nanotechnology, volume 15, number 9, September 2004.
Chris Dwyer, Moky Cheung, and Daniel J. Sorin. "Semi-empirical SPICE Models for Carbon Nanotube FET Logic." Fourth IEEE Conference on Nanotechnology (IEEE-Nano), August 2004.
Exercise Editor for: David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, third edition, Morgan-Kaufmann, August 2004.
Fred A. Bower, Paul G. Shealy, Sule Ozev, and Daniel J. Sorin. "Tolerating Hard Faults in Microprocessor Array Structures." International Conference on Dependable Systems and Networks (DSN), June 2004.
Jaidev P. Patwardhan, Chris Dwyer, Alvin R. Lebeck, and Daniel J. Sorin. "Circuit and System Architecture for DNA-Guided Self-Assembly of Nanoelectronics." Invited paper in Foundations of Nanoscience: Self-Assembled Architectures and Devices, April 2004.
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. "Using Speculation to Simplify Multiprocessor Design." International Parallel and Distributed Processing Symposium (IPDPS), April 2004.
Jaidev P. Patwardhan, Alvin R. Lebeck, and Daniel J. Sorin. "Communication Breakdown: Analyzing CPU Usage in Commercial Web Workloads." International Symposium on Performance Analysis of Systems and Software (ISPASS), March 2004.
Daniel J. Sorin, Mark D. Hill, and David A. Wood. "Dynamic Verification of End-to-End Multiprocessor Invariants." International Conference on Dependable Systems and Networks (DSN), June 2003.
Milo M. K. Martin, Pacia J. Harper, Daniel J. Sorin, Mark D. Hill, and David A. Wood. "Using Destination-Set Prediction to Improve the Latency/Bandwidth Tradeoff in Shared Memory Multiprocessors." 30th Annual International Symposium on Computer Architecture (ISCA), June 2003.
Tong Li, Alvin R. Lebeck, and Daniel J. Sorin. "Quantifying Instruction Criticality for Shared Memory Multiprocessors." 15th Symposium on Parallelism in Algorithms and Architectures (SPAA), June 2003.
Alaa R. Alameldeen, Milo M. K. Martin, Carl J. Mauer, Kevin E. Moore, Min Xu, Mark D. Hill, David A. Wood, and Daniel J. Sorin. "Simulating a $2M Commercial Server on a $2K PC." IEEE Computer, volume 36, number 2, February 2003.
Daniel J. Sorin, Jonathan L. Lemon, Derek L. Eager, and Mary K. Vernon. "Analytic Evaluation of Shared-Memory Architectures." Transactions on Parallel and Distributed Systems (TPDS), volume 14, number 2, February 2003.
Daniel J. Sorin. "Using Lightweight Checkpoint/Recovery to Improve the Availability and Designability of Shared Memory Multiprocessors." PhD Thesis, University of Wisconsin-Madison, August 2002.
Daniel J. Sorin, Manoj Plakal, Anne E. Condon, Mark D. Hill, Milo M. K. Martin, and David A. Wood. "Specifying and Verifying a Broadcast and a Multicast Snooping Cache Coherence Protocol." Transactions on Parallel and Distributed Systems (TPDS), vol. 13, number 6, June 2002.
Daniel J. Sorin, Milo M. K. Martin, Mark D. Hill, and David A. Wood. "SafetyNet: Improving the Availability of Shared Memory Multiprocessors with Global Checkpoint/Recovery." 29th International Symposium on Computer Architecture (ISCA), May 2002.
Milo M. K. Martin, Daniel J. Sorin, Mark D. Hill, and David A. Wood. "Bandwidth Adaptive Snooping." 8th International Symposium on High Performance Computer Architecture (HPCA-8), February 2002.
Alaa R. Alameldeen, Pacia J. Harper, Milo M. K. Martin, Carl J. Mauer, Daniel J. Sorin, Min Xu, Mark D. Hill, and David A. Wood. "Evaluating Non-deterministic Multi-threaded Commercial Workloads." Fifth Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-02), February 2002.
Milo M. K. Martin, Daniel J. Sorin, Harold W. Cain, Mark D. Hill, and Mikko H. Lipasti. "Correctly Implementing Value Prediction in Microprocessors that Support Multithreading or Multiprocessing." 34th International Symposium on Microarchitecture (MICRO-34), December 2001.
Milo M. K. Martin, Daniel J. Sorin, Anastassia Ailamaki, Alaa R. Alameldeen, Ross M. Dickson, Carl J. Mauer, Kevin E. Moore, Manoj Plakal, Mark D. Hill, and David A. Wood. "Timestamp Snooping:An Approach for Extending SMPs." 9th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-IX), November 2000.
Derek L. Eager, Daniel J. Sorin, and Mary K. Vernon. "AMVA Techniques for High Service Time Variability." ACM SIGMETRICS '00, June 2000.
Mark D. Hill, Anne E. Condon, Manoj Plakal, and Daniel J. Sorin. "A System-Level Specification Framework for I/O Architectures." 11th Annual Symposium on Parallel Algorithms and Architectures (SPAA), June 1999.
E. Ender Bilir, Ross M. Dickson, Ying Hu, Manoj Plakal, Daniel J. Sorin, Mark D. Hill, and David A. Wood. "Multicast Snooping: A New Coherence Method Using a Multicast Address Network." 26th Annual International Symposium on Computer Architecture (ISCA), May 1999.
Anne E. Condon, Mark D. Hill, Manoj Plakal, and Daniel J. Sorin. "Using Lamport Clocks to Reason About Relaxed Memory Models." 5th International Symposium on High Performance Computer Architecture (HPCA-5), January 1999.
Daniel J. Sorin, Vijay S. Pai, Sarita V. Adve, Mary K. Vernon, and David A. Wood. "Analytic Evaluation of Shared-Memory Systems with ILP Processors." 25th Annual International Symposium on Computer Architecture (ISCA), June 1998.
Daniel J. Sorin, Mary K. Vernon, Vijay S. Pai, Sarita V. Adve, and David A. Wood. "A Customized MVA Model for ILP Multiprocessors." Univ. of Wisconsin - Madison, Dept of Computer Sciences Technical Report #1369, April 1998.
Manoj Plakal, Daniel J. Sorin, Anne E. Condon, and Mark D. Hill. "Lamport Clocks: Verifying a Directory Cache-Coherence Protocol." 10th Annual Symposium on Parallel Algorithms and Architectures (SPAA), June 1998.