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\centerline{\Large{\bf ECE 261:CMOS VLSI Design Methodologies}}
\centerline{\large{Fall 2005}}
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{\centerline{\large Krish Chakrabarty}}
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\centerline{\large{Homework 1}}
\centerline{\large Assigned: September 12, 2005, Due: September 22, 2005 (start of class)}
{\flushleft{\bf Instructions}}: You are required to work on the homework on
your own. Please be legible and state all assumptions clearly. Show all work
in order to receive partial credit.
{\bf Problem 1}:
Sketch the transistor-level schematic of a CMOS 3-input XOR gate. Assume that
the inputs are available in both the complemented and uncomplemented forms. Your
design must consist of only a single stage of logic. \hfill [$10$]
{\bf Problem 2}:
A 3-input majority gate returns a true output if at least two of its
inputs are true. A minority gate is its complement. Sketch a transistor-level
schematic of a 3-input minority logic gate using a single-stage of logic.
\hfill [$10$]
{\bf Problem 3}:
Design a pull-down circuit
corresponding to the pull-up circuit shown below for implementing the function
$f$. \hfill[10]
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{\bf Problem 4}: Textbook, Page 108, Problem 2.2 (b) Textbook, Page 109, Problem 2.8 (c) Textbook, Page 111, Problem 2.22. \hfill[$10+5+5=20$]
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