ECE 261: CMOS VLSI Design Methodologies, Fall 2009


Lab 1

Assigned: September 17, Due: October 3

The purpose of this lab assignment is to become familiar with Mentor Graphics design tools and the design rules. This assignment is to design and verify and simulate using ELDO or Modelsim a 3-input AND gate. Copy the EE261 library INV and NAND cells to your library. To make the schematic and layout, paste an instance of an inverter and nand gate in the design and connect them together (Use the 'i' key in the schematic and F5 key on the layout to paste new instances, connect them together on the layout using the 'p' key). Make sure that it conforms to all the calibre design rules, i.e. passes DRC and LVS.

You are required to show your design and simulation to the TA and demonstrate that it passes DRC and LVS and functions like a 3 Input And gate. The deadline for doing this is Oct 3. The TA will be holding office hours in the lab based on the schedule posted on the web page, so please demo your design as soon as you can. You are also advised to start early on your labs so that you don't face unforeseen problems with Mentor licenses and server crashes