• Lab report due date: The date you start your next lab exercise (i.e., lab 5)

Warning! The analog input to the ADC must be constrained to within 0 and VCC. A voltage  of ONLY 100mV in excess of these bounds will fry the ADC! Pay close attention to how to wire up power supplies for this lab to minimize chances of frying the converters.

Do not power up your circuit until a TA has checked it! 

First, create a test circuit with a 50k potentiometer. Connect the ends of the potentiometer (not the tap) to the 5V (be precise!) and GND rails. You may need to bend the PCB mounting tabs on the potentiometer to fit it into the breadboard (use pliers). Test the circuit with the oscilloscope by varying the position of the potentiometer and measuring the voltage (w.r.t. GND) at its tap. Create two more circuits like this one and verify that they work correctly.

Disconnect the power from your setup prior to wiring up the ADC. (Leave the supply set to 5V).

Next, setup the ADC for continuous conversion by wiring EOC (pin 7) to START (pin 6). This establishes a cycle-after-cycle sampling mode. The ADC0808's conversion process can be controlled more precisely but this is beyond today's lab. After power-up, a momentary pulse on START (pin 6) may be required to kick start the conversion process. Use a SPDT switch tied to Vdd on one side and EOC on the other, with the common tied to START. To kickstart the ADC switch the SPDT to Vdd and then back to allow the EOC signal to trigger the next conversion(s). Transients during power-up will often kickstart this process, so this switch is just backup.

We will be using the ADC as a ratiometric converter, illustrated in Figure 9 of the datasheet. Tie Vref(+) (pin 12) to Vcc (pin 11) (the analog equivalent of Vdd) and Vref(-) (pin 16) to GND (pin 13.) This creates a common analog and digital supply. For reference, high bandwidth low noise (i.e., sensitive) measurements require separate analog and digital supplies. (This lab requires neither). Supply a 5V, 650 kHz square wave (50% duty cycle) to the clock input (CLOCK, pin 10).

Select three inputs (from IN0 to IN7) to monitor the voltages at the three potentiometer taps. Use a dip switch block connected through pull-up resistors (100k) or a SPDT switch block on the "ADD A", "ADD B", and "ADD C" address lines to select which sensor position to display. The ALE (address latch enable) signal must transition from low-to-high to latch a new address (use a dip or SPDT switch for this whenever you change the address).

Using a logic analyzer, observe the 8-bit digital output for each sensor. Notice how it varies with input voltage as a function of the angular position of the potentiometer. Obtain a logic analyzer trace for each sensor set ~180deg. apart (e.g., 0deg. and 180deg.) [the PTV111 potentiometer has a 300deg. mechanical swing]

Given the linear relationship between analog input voltage and digital output value, is this result sensible?

How would you convert the digital output value into a sensor position (e.g., in degrees)? [I.e., what's the formula?]

Using VHDL (i.e., not schematic capture!), design in Quartus a digital system that takes as input an 8-bit unsigned quantity (namely, the output of the ADC) and produces the units and tenths digit of the corresponding sensor voltage (between 0.0 and 5.0). Render the result on the seven-segment displays on the Altera DE2 board. If you are able to reuse any designs from lab 3, great!

You may find it helpful to consider the units and tenths digits separately. Using the linear relationship between the digital output 'D' and the analog input voltage, it is easy to see that the units digit equals 'D'/51 (using integer division, i.e. the result is rounded towards zero). Furthermore, the tenths digit equals ((D%51)*10)/51, where the modulus (%) operator denotes the remainder of a division operation.

To perform these computations, you can use a divider circuit provided by Quartus. While inside of a block diagram, place an lpm_divide megafunction. A wizard will be instantiated. Instruct it to generate VHDL code for the divider, then specify the input widths (consider the magnitude of the numerator and denominator in specifying these widths). After creating an instance of the divider, you can reference it in VHDL code by means of a PORT MAP statement. TAs will help you with this wizard.

How might you redesign the circuit to simplify the display process? Why? (e.g., choice of Vdd?) [HINT: by an approximation and/or a convenient choice of Vdd=3.984 ... if we ignore the operating range for the ADC! It's a bit more complicated if we stick to the required 4.5V < Vdd < 6.0V for this ADC.] Consider where the '51' in the denominator came from when we were using Vdd=5.0 (and an 8 bit max. value)?

Describe how to improve the accuracy of your approximation. [HINT: use more bits and describe how.]