Pollution Control Caching
Stephen J. Walsh and John A. Board, Jr.
Abstract
The bandwidth mismatch of today's high speed processors and standard DRAMS is between a factor of 10 to 50.
From 1995 to the year 2000 this mismatch is expected to grow to three orders of magnitude, necessitating
greater emphasis for on-chip caches. However, the cost of on-chip memory is largely a function of the chip
area it requires. Today, these on-chip caches typically consume from 20\% to 50\% of the total chip area; clearly,
only so much chip area can be devoted to caches. Any technique
which can maintain memory performance and reduce chip area requirements is extremely important.
In this paper we
present two novel cache architectures called Pollution Control Caching (PCC) and
Pollution Control Caching plus Victim Buffering (PCC+VB).
We have used trace driven simulation to obtain miss ratio statistics on a variety of workloads
for direct mapped, 2-Way, 4-Way, 8-Way, PCC, and PCC+VB cache architectures.
We developed analytical models of the expected clock cycles per instruction ({\bf E}[CPI]) for
each architecture and cache size studied.
These models incorporate provisions to model the effect that on-chip cache size has on access time,
and the effect that this and different main memory latencies have on the {\bf E}[CPI]. In addition,
we developed Petri Net models of each architecture and solved them for the {\bf E}[CPI] using the SPNP
package. These models were parameterized with the results of the trace driven simulation.
Chip area models were also developed for each architecture and used as a basis for comparison.
Finally, we used ANOVA techniques to better quantify the differences in the miss rate performance of the cache
sizes and cache architectures studied.
Our research has shown that, given the constraints of our design space,
small PCC+VB equipped caches can match the
miss rate performance and {\bf E}[CPI] of direct mapped caches that are greater than four
times their size.
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