Vikram Iyengar

List of Publications

Books and book chapters

• K. Chakrabarty, V. Iyengar and A. Chandra, Test Resource  Partitioning for System-on-a-Chip, Kluwer Academic Publishers, Norwell,  MA, 2002.
• V. Iyengar and E.M. Rudnick, Design verification, in The VLSI Handbook, W-K. Chen (ed.), CRC Press, Boca Raton, FL and IEEE Press, New York, NY, 2000.

Journal articles

• V. Iyengar and K. Chakrabarty. System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.  IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, September 2002, to appear.
• V. Iyengar and K. Chakrabarty. Test bus sizing for system-on-a-chip. IEEE Trans. Computers, vol. 51, pp. 449-459, May 2002.
• V. Iyengar, K. Chakrabarty and E. J. Marinissen. Test wrapper and test access mechanism co-optimization for system-on-a-chip. J. Electronic Testing, vol. 18, no. 2, pp. 213-230, April 2002.
• V. Iyengar, H. Date, M. Sugihara and K. Chakrabarty. Hierarchical IP  protection using partially-mergeable cores. IEICE Trans.  Fundamentals of Electronics, Communications and Computer Sciences, vol. E84-A, no. 11, pp. 2632-2638, Nov 2001.
• K. Chakrabarty, B. T. Murray and V. Iyengar, Built-in test pattern generation using twisted ring counters, IEEE Trans. VLSI Systems, vol. 8, no. 5, pp. 633-636, Oct 2000.
• T-C. Chang, V. Iyengar and E. Rudnick, A biased-random instruction generation environment for architectural verification of pipelined microprocessors, J.Electronic Testing: Theory and Applications, vol. 16, no. 1 and 2, pp. 13--27, Feb/April 2000.
• V. Iyengar, K. Chakrabarty and B. T. Murray, Deterministic built-in self testing of sequential circuits using precomputed test sets, J. Electronic Testing: Theory and Applications, vol. 15, pp. 97-114 Aug/Oct 1999.
• V. Iyengar, K. Chakrabarty and B. T. Murray, Huffman encoding of test sets for sequential circuits, IEEE Trans. Instrumentation and Measurement, vol. 47, no. 1, pp. 21-25, Feb 1998.
• V. Iyengar and K. Chakrabarty, An efficient finite-state machine implementation of Huffman decoders, Information Processing Letters, vol. 64, no.6, pp. 271-275, Jan 1998.

Conference papers

• V. Iyengar, K. Chakrabarty and E.J. Marinissen. Recent Advances in Test Planning for Modular Testing of Core-Based SOCs. Proc. Asian Test Sympoium, pp. 320-325, 2002.
• V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty. Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints. Proc. IEEE International Test Conference, pp. 1159-1168, 2002.
• E. J. Marinissen, V. Iyengar and K. Chakrabarty. A set of benchmarks for modular testing of SOCs. Proc. IEEE International Test Conference, pp. 519-528, 2002.
• S. Koranne and V. Iyengar. On the use of k-tuples for SOC test scheduling. Proc. IEEE International Test Conference, pp. 539-538, 2002.
• V. Iyengar, K. Chakrabarty and E. J. Marinissen. Integrated wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs. Proc. IEEE/ACM Design Automation Conference, pp. 685-690, 2002.
• V. Iyengar, K. Chakrabarty and E. J. Marinissen. On using rectangle packing for wrapper/TAM co-optimization. Proc. IEEE VLSI Test Symposium, pp. 253-258, 2002.
• V. Iyengar, K. Chakrabarty and E. J. Marinissen. Efficient wrapper/TAM co-optimization for large SOCs. Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 491-498, 2002.
• V. Iyengar, K. Chakrabarty and E. J. Marinissen. Test wrapper and test access mechanism co-optimization for system-on-a-chip. Proc. IEEE Int. Test Conf., pp. 1023--1032, 2001.
• V. Iyengar and K. Chakrabarty, Precedence-based, preemptive and power-constrained test scheduling for system-on-a-chip, IEEE VLSI Test Symposium, pp. 368-374, 2001.
• H. Date, V. Iyengar, K. Chakrabarty and M. Sugihara, Mathematical Modeling of Intellectual Property Protection Using Partially-Mergeable Cores, International Conference on Parallel and Distributed Processing Techniques and Applications, 2000.
• K. Chakrabarty, B. T. Murray and V. Iyengar, Built-in test pattern generation for high-performance, core-based circuits using twisted ring counters, IEEE VLSI Test Symposium, pp. 22-27, 1999.
• V. Iyengar, K. Chakrabarty and B. T. Murray, Deterministic built-in self testing of sequential circuits using precomputed test sets, Proc. IEEE VLSI Test Symposium, pp. 418-423, 1998.
• V. Iyengar, K. Chakrabarty and B. T. Murray, Test set encoding for efficient sequential circuit testing, Proc. Instrumentation and Measurement Technology Conference, pp. 1442-1447, 1997.

Workshop presentations

A. Chandra, S. Schweizer, V. Iyengar and K. Chakrabarty. A Unified Approach for SOC Test Resource Partitioning Using Test Data Compression and TAM Optimization. Test Resource Partitioning Workshop, pp. 4.4-1 - 4.4-7, 2002.

V. Iyengar, S. Goel, E. J. Marinissen and K. Chakrabarty. On optimization of test resources for multi-site testing of SOCs. North Atlantic Test Workshop, 2002.

V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty. Test resource optimization for multi-site testing of embedded-core-based SOCs using ATE with memory depth constraints. European Test Workshop, 2002.

V. Iyengar and K. Chakrabarty. TAM width sizing and test scheduling to reduce tester data volume for SOCs. International Test Synthesis Workshop, 2002.

V. Iyengar and K. Chakrabarty. Iterative test access mechanism optimization for system-on-a-chip, IEEE  International Workshop on Testing Embedded Core-Based System Chips, 2001.

V. Iyengar and K. Chakrabarty, Test wrapper and test access mechanism co-optimization for system-on-a-chip, IEEE  European Test Workshop , 2001.

V. Iyengar, M. Sugihara, H. Date and K. Chakrabarty, Intellectual property protection using partially-mergeable cores, IEEE Testing Embedded Core Systems Workshop, pp. 4.3.1-4.3.6, 2000.

V. Iyengar, K. Chakrabarty and B. T. Murray, Built-in self testing with complete fault coverage and practical test application time, IEEE North Atlantic Test Workshop, 1997.

Poster presentations

• V. Iyengar, A. Chandra, S. Schweizer, and K. Chakrabarty. A Unified Approach for SOC Testing Using Test Data Compression and TAM Optimization. Design Automation and Test in Europe Conference, 2003, to appear.

Web articles

V. Iyengar, A. Chandra and K. Chakrabarty. University research in system-on-a-chip testing, EDA Vision (www.edavision.com), vol. 1, issue 3, Sept 2001.