|Professor Daniel J. Sorin|
|The objective of this course is to learn how computers work, focusing on how the computer hardware executes the software.|
|The course focuses on: instruction sets, assembly language programming, basic digital logic design, processor design, memory system design, and input/output.|
|Prerequisites: ECE 110 (used to be ECE 27) and CS 201 (used to be CS 100)|
|Class Location and Hours|
Class meets Monday/Wednesday/Friday from 10:05am - 11:20am.
Friday's class is a recitation.
Location: Hudson 212
|Instructor, Teaching Assistant, and News Group|
This is a large class, which means that students should contact other sources of information before, if necessary, contacting the professor.
* The first option for finding help is this website.
* The second option for finding help is the outstanding group of teaching assistants for this course. Either email them (via the Sakai forum) or go to their office hours. Questions on the Sakai forum may get answered by a TA, a fellow classmate, or the professor.
Graduate Teaching Assistant: Ralph Nathan (email@example.com), Weds 1-2p @ Hudson 202A
Undergraduate Teaching Assistants:
Ashley Chou, Mon 6:15-7:15p @ Link
Oliver Fang, Tues 12-1p @ Link
James Hong, Fri 1-2p @ Link
Michele Reshef, Weds 3-4p @ Hudson LINK (room near front door of Hudson)
Jennifer Villa, Mon 4:30-5:30
* If you need to contact the professor, please email him or come to his office hours:
Professor Daniel J. Sorin
Office: 209C Hudson Hall
Office Hours: Tues 1-2p, Thurs 2-3p
Email: sorin AT ee DOT duke DOT edu (email subject must begin with ECE250)
|David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 4th edition, Morgan-Kaufmann.|
|Please do not get the "ARM" edition or the "Revised Printing" -- for some reason, the publisher has created several flavors of this book.|
|Assignments and Grading|
|This course will require readings from the textbook, pencil and paper problems, programming assignments, and digital logic designs.|
Students are responsible for:
|Deadlines will be enforced except under extreme
circumstances. Anything turned in late will incur a 10% penalty
per day late (e.g., from due date until 24 hours late is 10%
off). I would prefer that you turn in something not quite done on the due date
rather than waiting until after the deadline to try to finish
Start assignments and projects EARLY so that you don't get stuck at the end!
|Academic Misconduct: I will not tolerate academically dishonest work. This includes cheating on the homework and exams.|
|I will refer all suspected cases of cheating to the Duke Undergraduate Judicial Board.|
|Refer to the Duke Undergraduate Honor Code or to the instructor if you have any questions about misconduct.|
|Topics, Lecture Notes, and Reading Assignments|
I will post lecture notes (in PDF format) shortly before I cover them in class. Please bring them to class. Click on topic title for link to notes.
Do not think that you can read the notes instead of attending class. You will miss a LOT of course material if you miss class.
Homework #1 (From C to binary), due Monday, Sept 10
Homework #2 (Assembly programming), due Wednesday, Sept 26
Homework #3 (Digital logic design), due Friday, Oct 12
Homework #4 (Processor core design), due Weds, Oct 31
Homework #5 (Memory systems), due Wednesday, Nov 21
Homework #6 (I/O), due TBD
Homework #7 (Pipelining & Multicore)
This is a VERY tentative schedule which may change depending on time constraints and which days the instructor will be out of town.
From C to binary
C programming: comparison to java, using libraries, compiling, etc.
From C to binary
|From C to binary||C programming: memory management, debugging with gdb|
|Sep 10||Assembly language||Assembly language||Assembly programming examples / Using SPIM|
|Sep 17||Assembly language||Assembly language||Assembly programming examples: focus on calling conventions|
|Sep 24||Intro to digital logic design||Combinational logic||
Digital design examples / Using Logisim
|Oct 1||Sequential logic||Sequential logic||Midterm #1 (does not include digital logic design)|
|Oct 8||Functional units||Datapath design||Using Logisim for larger projects|
|Datapath design||Optional: Advanced functional unit design|
|Oct 22||Datapath design||Exceptions/Interrupts/Syscalls||TBD|
|Oct 29||Memory hierarchies||Caches||Cache operation examples|
|Nov 5||Caches||Virtual memory||Midterm #2 (does not include memory systems)|
|Nov 12||Virtual memory||Virtual memory||Virtual memory operation examples|
|Nov 26||I/O||Multicore processors||Sun's Niagara multicore processor|
Pipelined processor cores
|Pipelined processor cores||review for final exam|
-------- EXAM WEEK --------