ECE 552 / CPS 550

Advanced Computer Architecture I

Fall 2021

Professor Daniel J. Sorin

                  

 Objectives

 

The objective of this course is to learn the fundamental aspects of computer architecture design and analysis.

The course focuses on processor design, pipelining, superscalar, out-of-order execution, caches (memory hierarchies), virtual memory, storage

systems, and simulation techniques. Advanced topics include a survey of parallel architectures and future directions in computer architecture.

Prerequisites: ECE/CS 250 or ECE 550 or consent of instructor

 

Class Location and Hours

 

Class meets Monday/Wednesday/Friday from 10:15-11:05 am.

Location:  LSRC A-247

 Instructor and Teaching Assistants

 

Professor Daniel J. Sorin

Office: Wilkinson 403

Office Hours: TBD

Email: sorin AT ee DOT duke DOT edu 

 

Graduate Teaching Assistant: Shiyu Li  (shiyu DOT li AT duke DOT edu)

 

Required Textbooks

 

Computer Architecture: A Quantitative Approach, 5th edition, by Hennessy and Patterson

A Primer on Memory Consistency and Cache Coherence, 2nd edition, by Nagarajan, Sorin, Hill, and Wood.  (free PDF download from Duke IP addresses)

 

 Assignments and Grading

 

This course will require readings from the textbooks and from selected research papers.  While you will not be quizzed on readings, you

should still be certain to have read them before class so that you can learn from the class.  And, to appeal to your practical side, all readings are

fair game for the exams.  Added bonus: you will be better at reading research papers at the end of this class than at the beginning.

Students are responsible for:

Late policy for paper reports, homework, and project (except for dean's excuse or STINF):

        Paper reports: No late paper reports will be accepted.  Grade will be 0.

        Homework: late by <24 hours = take earned score and divide by 2 -- this applies to entire assignment (not per question)

                           late by >=24 hours =  Grade will be 0.

        Project: No late projects will be accepted.  Grade will be 0.

 

Pandemic Issues: By default, there are no exceptions or extensions in my classes. However, because of the pandemic, there may be new pandemic-related reasons for exceptions and/or extensions. Please contact me if these arise.

 

Academic Misconduct: I will not tolerate academically dishonest work.  This includes cheating on the exams and plagiarism on the project.  

Be careful on the project to cite prior work and to give proper credit to others' research. 

Refer to the Duke Undergraduate Honor Code or to the instructor if you have any questions about misconduct.

Academic misconduct policies will NOT be affected in any way by the pandemic.

 

 Topics, Lecture Notes, and Reading Assignments (still in flux!!)

 

I will post lecture notes (in PDF format) on Sakai shortly before I cover them in class.  Click on topic title for link to notes.

Readings in blue will be provided by the instructor (click on links below for PS or PDF).

Topic

Reading Assignments

Course Introduction & Computer Performance

H/P Chapter 1;
"Instruction Sets and Beyond: Computers, Complexity, and Controversy"

Pipelined Processor Cores
   

H/P Appendix C; 
"The Optimal Logic Depth Per Pipeline Stage is 6 to 8 FO4 Inverter Delays"

Superscalar (wide) Processor Cores 

H/P Chapter 3

Software/Static Exploitation of Instruction Level Parallelism
  

H/P Chapter 3;
"EPIC: Explicitly Parallel Instruction Computing"

Hardware/Dynamic Exploitation of Instruction Level Parallelism
    

H/P Chapter 3;  
"The Microarchitecture of the Pentium 4 Processor"
;

"Complexity-Effective Superscalar Processors"

"Checkpoint Processing and Recovery: Towards Scalable Large Instruction Window Processors"

Exploiting Data-level Parallelism: SIMD, Vectors, and GPUs

H/P Chapter 4;
"NVidia Tesla: A Unified Graphics and Computing Architecture" 

Advanced Memory System Design

H/P Chapter 2 (remedial material in Appendix B);
"An Adaptive, Non-Uniform Cache Structure for Wire-Dominated On-Chip Caches"

"The ZCache: Decoupling Ways and Associativity"

"Exceeding the Dataflow Limit via Value Prediction"

Exploiting Thread-Level Parallelism: Multithreading, Multicore, and Multiprocessors

         

H/P Sections 5.1 and 3.12; 
"Power: A First-Class Architectural Design Constraint"


"Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor"


"Multiscalar Processors"


"Single-ISA Heterogeneous Multi-Core Architectures for Multithreaded Workload Performance"

"Amdahl's Law in the Multicore Era"

Shared Memory, Memory Consistency, and Cache Coherence

Primer on Consistency and Coherence: Chapters 1-8

TBD

Interconnection Networks

TBD

 

 Homework

Homework policy: Homework must be done individually.  Violations of this rule will be considered academic misconduct.

Homework assignments will be posted on Sakai.

 Paper Reports

Paper report policy: Paper reports must be done individually. Each report should be approximately 1 page long.

Each paper report grade is out of 2 points: Good report = 2, poor report = 1, no report = 0.


A report must include all of the following: contributions of paper (what unmet need is this paper addressing?), a list of the paper's strengths and weaknesses (not including grammar or text issues!), and at least one question you have after reading it. Do not simply regurgitate the abstract.

 Project

The course project will be performed either individually or in groups of 2 or 3. 

Typical projects involve implementing and exploring a microarchitectural idea using a simulator such as SimpleScalar.  See Prof. Sorin for project guidelines and ideas.

Project proposals (2 pages max!!): Proposals due Friday, Oct 22.  Proposals must contain the following information:

Project reports (15 pages max!!): Reports due Monday, Nov 22.  No exceptions!

 Schedule (tentative)

This is a tentative schedule which may change depending on time constraints. Also, pandemic.

Week

Monday

Wednesday

Friday

Aug 23

Prof. Sorin out of town NO CLASS

Intro/Review

Review

Aug 30

Goals

Pipelining

Pipelining

Sept 6

Pipelining

Superscalar

Superscalar

Sept 13

Static ILP

Static ILP

Static ILP

Sept 20

Static ILP

Dynamic ILP

Dynamic ILP

Sept 27

Dynamic ILP

Dynamic ILP

Dynamic ILP

Oct 4

FALL BREAK

Dynamic ILP

Dynamic ILP

Oct 11

Dynamic ILP

REVIEW FOR MIDTERM

MIDTERM EXAM

Oct 18

SIMD/Vector/GPU

SIMD/Vector/GPU

SIMD/Vector/GPU

Project Proposals Due

Oct 25

Memory Systems

Memory Systems

Memory Systems

Nov 1

Memory Systems

Memory Systems

TLP/Multithreading

Nov 8

TLP/Multithreading

Shared Memory

Consistency

Nov 15

Consistency

Coherence

Coherence

Nov 22

Coherence

Project Reports Due

THANKSGIVING

Nov 29

REVIEW FOR FINAL

READING PERIOD

READING PERIOD

Dec 6

READING PERIOD

FINALS WEEK

FINALS WEEK

Dec 13

FINALS WEEK