|ECE 250 / CS 250|
|Professor Daniel J. Sorin|
|The objective of this course is to learn how computers work, focusing on how the computer hardware executes the software.|
|The course focuses on: instruction sets, assembly language programming, basic digital logic design, processor design, memory system design, and input/output.|
|Prerequisites: Everyone must have CS 201 (used to be CS 100). ECE majors must also have ECE 110 (used to be ECE 27).|
|Class Location and Hours|
Class meets Monday/Wednesday/Friday from 10:20am - 11:10am at Soc Sci 139.
Recitations are on Tuesday.
|Instructor, Teaching Assistant, and News Group|
This is a very large class, which means that students should contact other sources of information before, if necessary, contacting the professor.
* The first option for finding help is this website.
* Then check the course's Sakai and Piazza sites.
* The third option for finding help is the outstanding group of teaching assistants for this course. Either email them (via the Piazza forum) or go to their office hours. Questions on the Piazza forum may get answered by a TA, a fellow classmate, or the professor.
* Please contact the professor only for those issues that cannot be handled by anyone else.
Graduate Teaching Assistants:
Luwa Matthews (email@example.com)
Undergraduate Teaching Assistants:
* If you need to contact the professor, please email him or come to his office hours:
Professor Daniel J. Sorin
Office: 209C Hudson Hall
Office Hours: TBD --- email me if you have class at both of these times and wish to meet with me
Email: sorin AT ee DOT duke DOT edu
|David A. Patterson and John L. Hennessy. Computer Organization and Design: The Hardware/Software Interface, 5th edition, Morgan-Kaufmann.|
|Please do not get the "ARM" edition or the "Revised Printing" -- for some reason, the publisher has created several flavors of this book.|
|Assignments and Grading|
|This course will require readings from the textbook, pencil and paper problems, programming assignments, and digital logic designs.|
Students are responsible for:
Late homework policy -- NO exceptions, NO extensions (except in case of dean's excuse)
0-24 hours late: 10% penalty
24-48 hours late: 20% penalty
>48 hours late: NO CREDIT
Start assignments and projects EARLY so that you don't get stuck at the end!
|Academic Misconduct: I will not tolerate academically dishonest work. This includes cheating on the homework and exams.|
|I will refer all suspected cases of cheating to the Duke Undergraduate Judicial Board.|
|Refer to the Duke Community Standard or to the instructor if you have any questions about misconduct.|
|Topics, Lecture Notes, and Reading Assignments|
I will post lecture notes (in PDF format) shortly before I cover them in class. Please bring them to class. Click on topic title for link to notes.
Do not think that you can read the notes instead of attending class. You will miss a LOT of course material if you miss class.
Remote access to Linux machines.
This is a VERY tentative schedule which may change depending on time constraints and which days the instructor will be out of town.
Unix and text editing
From C to binary
|C programming: Intro||From C to binary||From C to binary|
|Sept 8||From C to binary||C programming: pointers and memory management||Assembly||Assembly
Due: HW #1 (C programming)
|Sept 15||Assembly||Assembly programming examples / Using SPIM||Intro to digital logic / combinational logic||Sequential logic|
|Sept 22||Sequential logic||
Assembly programming examples: focus on calling conventions
Due: HW #2 (Assembly)
|Sept 29||Datapath design||Digital design examples / Using Logisim||Datapath design||Midterm #1 (does not include digital logic design)|
|Oct 6||Exceptions/interrupts/syscalls||Using Logisim for larger projects||Memory hierarchies||Caches|
|Oct 20||Caches||Cache operation examples||Virtual Memory||Virtual Memory|
|Oct 27||Virtual Memory||review for Midterm #2||I/O||Midterm #2 (does not include memory systems)|
|Nov 3||I/O||Virtual memory operation examples||I/O||Pipelined cores|
|Nov 10||Pipelined cores||Cache+virtual memory examples||
|Nov 17||Pipelined cores||Pipelined operation examples||Multicore||Multicore|
Sun's Niagara multicore processor
|review for final exam||In-class study of modern processors||review for final exam|