Meng Zhang 4th Year Ph.D. Student Department of Electrical and Computer Engineering Duke University 213B Hudson Hall, Research Dr. Durham, NC 27708, USA Email: mz28@duke.edu Tel: (919)660-5164

About Me

Hi, I am Meng Zhang, a 4th year Ph.D. student from the Department of Electrical and Computer Engineering at Duke University. My advisor is Dr. Daniel J. Sorin. I obtained my M.S. and B.S. degrees from Beihang University in China in 2008 and 2005, respectively.

Research Interests

My current research focuses on scalable verifiable cache coherence design, especially for heterogeneous systme, such as systems with CPUs and GPUs. Our main goal is to make the cache coherence protocol more amenable to verificaiton while still maintain scalability with regard to performance/power/area etc. I also have interest in fault tolerant computer architectures and reliable system design.

Publications

• Fractal Consistency: Architecting the Memory System to Facilitate Verification [pdf]
  Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin.
  Computer Architecture Letters, volume 9, number 2, July-December 2010


• Fractal Coherence: Scalably Verifiable Cache Coherence [pdf]
  Meng Zhang, Alvin R. Lebeck, and Daniel J. Sorin.
  43rd International Symposium on Microarchitecture (MICRO 2010), December 2010.


• Analyzing Formal Verification and Testing Efforts of Different Fault Tolerance Mechanisms [pdf]
  Meng Zhang, Anita Lungu, and Daniel J. Sorin.
  24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFTS 2009), October 2009.

Work Experience

• 08/2011-11/2011, Research Intern, NVIDIA Research

  Design and implement a hardware cache coherence engine on next generation GPU infrastructure under Steve Keckler and James Balfour

Teach Experience

• Fall 2009: Teaching Assistant of ECE 252 Advanced computer architecture

• Fall 2010: Teaching Assistant of ECE 152 Introduction to Computer Architecture

Invited Talks

• "Fractal Coherence: Scalably Verifiable Cache Coherence"

  -- Intel Corporation (Hudson, MA), Feb. 2011

  -- CSAIL Angstrom Seminar, Massachusetts Institute of Technology, Feb. 2011

  -- Computer Engineering Seminar, North Carolina State University, Feb. 2011

• "Verification-aware Architecture Design"

  -- CSAIL Angstrom Student Lunch Seminar, Massachusetts Institute of Technology, Feb. 2011

Previous Projects

• Hardware Cache Coherence for CPU/GPU Heterogeneous Systems

  Explored the design space of hardware cache coherence on a heterogeneous system with CPUs and GPUs to see what design options is optimal regarding performance/power/area etc. The study is based on an innovative infrastructure in which CPUs and GPUs have a unified memory space.

• Verification-aware Memory System Design for Multi-core Processors

  Designed subsystems of Multi-core processors in a special way (fractal) to ease design verification. The subsystems we have designed include cache coherence protocols and memory consistency models. By leveraging fractal idea, we enable the verification of any N-node system using induction.

  Here is the specification of an example cache coherence protocol using our method TreeFractal Protocol

• Pre- & Post-Silicon Verification Effort Analyses for Fault Tolerance Mechanisms

  Analyzed the pre-fabrication design verification effort and post-fabrication chip testing effort of different fault-tolerant mechanisms. These fault tolerant mechanisms include DMR, TMR, Re-execution and parity code. We found that Re-execution is the most efficient mechanism when considering formal verification and testing efforts together.

• CCA-Argus: Core Cannibalization Architecture with Error Detection

  Implemented an error detection mechanism (Argus) on Core Cannibalization Architecture (CCA), a self-reconfiguration mechanism for multicore processors with hard faults.

Last updated: 02/09/2012