Instructor: Prof. Krish Chakrabarty
Office Hours: Tues, Thurs 11:30 AM to 12:30 PM, 161 Hudson Hall (remote until January 18), or by appointment
Class hours and classroom: Tues, Thurs 10:15 AM to 11:30 AM, Room: 222 Hudson Hall (Remote till January 18)
Textbook: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Springer, 2005.
Course TA: Jayeeta Chaudhuri
Office hours and location: Tuesday and Thursday 5-6 PM, in 161 Hudson Hall (remote until January 18).
Prerequisites: Senior/graduate standing, course in logic design. Some exposure to full-custom VLSI design, an introductory course in computer organization, basic knowledge of design and analysis of algorithms, and basic programming skills are desirable.
Please refer to this PDF file for information about lecture schedule
Course Outline: This course will examine in depth the theory and practice of fault analysis, test generation, and design for testability for digital VLSI circuits and systems. Testing tools and systematic design-for-test (DFT) methodologies are necessary to handle design complexity, ensure reliable operation, and achieve short time-to-market. The topics to be covered in the course include: fault modeling; fault simulation; test generation algorithms; testability measures; design for testability and scan design; built-in self-test, delay testing; wafer-level burn-in and test; memory testing; system-on-a-chip test; test compression. Grading will be based on homework assignments, two in-class exams, and a term project, which may be either a research survey, testing of a chip from a previous class or research project that has been fabricated using MOSIS, or a software implementation of a test methodology. Students will get a chance to use commercial DFT tools such as EncounterTest from Cadence, Fastscan from Mentor Graphics, and Tetramax from Synopsys. Current research issues, including topics suitable for M.S. and Ph.D. research will also be discussed.
For an overview of the VLSI Testing field and the academic and professional community associated with it, please look up the IEEE Test Technology Technical Council (TTTC) website.
Homeworks and Exams: There will four evenly-spaced homeworks in the form of problem sets. These will be based on the lecture material. Two in-class exams, scheduled for February 22 and April 12, respectively, will test basic understanding of the concepts presented in the class.
Grading Policy: Four homeworks-20%, Exam I-25%, Exam II- 25%, Project-30%.
Note that there will be a penalty of 10% per day on late homework and lab
submissions. Late homework and lab submissions will not be accepted after
three days. Please do not try these excuses! Please be legible and clear so that your homework is readable.