ECE 538: VLSI System Testing, Spring 2014

Instructor: Prof. Krish Chakrabarty
Office: 2513 CIEMAS
Ph: 660-5244
Office Hours: Tues, Thurs 11:30 AM to 12:30PAM, or by appointment

Class hours and classroom: Tues, Thurs 10:05 AM to 11:20 AM, Room: 218 Hudson Hall

Textbook: M. L. Bushnell and V. D. Agrawal, Essentials of Electronic Testing, Springer, 2005.

Course TA: Mukesh Agrawal
Office hours: Monday, Thursday 1:30-2:30 pm, Room 160 Hudson Hall

Prerequisites: Senior/graduate standing, course in logic design. Some exposure to full-custom VLSI design, an introductory course in computer organization, basic knowledge of design and analysis of algorithms, and basic programming skills are desirable.

Please refer to this PDF file for information about lecture schedule

Course Outline: This course will examine in depth the theory and practice of fault analysis, test generation, and design for testability for digital VLSI circuits and systems. Testing tools and systematic design-for-test (DFT) methodologies are necessary to handle design complexity, ensure reliable operation, and achieve short time-to-market. The topics to be covered in the course include: fault modeling; fault simulation; test generation algorithms; testability measures; design for testability and scan design; built-in self-test, delay testing; wafer-level burn-in and test; memory testing; system-on-a-chip test; test compression. Grading will be based on homework assignments, two in-class exams, and a term project, which may be either a research survey, testing of a chip from a previous class or research project that has been fabricated using MOSIS, or a software implementation of a test methodology. Students will get a chance to use commercial DFT tools such as EncounterTest from cadence, Fastscan from Mentor Graphics, and Tetramax from Synopsys. Current research issues, including topics suitable for M.S. and Ph.D. research will also be discussed.

For an overview of the VLSI Testing field and the academic and professional community associated with it, please look up the IEEE Test Technology Technical Council (TTTC) website.

Homeworks and Exams: There will four evenly-spaced homeworks in the form of problem sets. These will be based on the lecture material. Two in-class exams, tentatively scheduled for March 18 and April 15, respectively, will test basic understanding of the concepts presented in the class.

Grading Policy: Four homeworks-20%, Exam I-25%, Exam II- 25%, Project-30%.

Note that there will be a penalty of 10% per day on late homework and lab submissions. Late homework and lab submissions will not be accepted after three days. Please do not try these excuses !

Fastscan Tutorial (Prepared by Mahmut Yilmaz)

Synopsys Tutorial (Prepared by Himanshu Thapliyal)


Project Handout

Here are copies of slides used in class (PDF format):

Lecture notes for 01/09/14

Lecture notes for 01/14/14

Lecture notes for 01/16/14

Lecture notes for 01/21/14

Lecture notes for 01/23/14

Lecture notes for 01/30/14

Lecture notes for 02/04/14

Lecture notes for 02/06/14

Lecture notes for 02/11/14

Lecture notes for 02/13/14 and 02/18/14

Additional materials for reading: 1) Tutorial on scan operation, 2) Boundary scan tutorial

Lecture notes for 02/25/14

Lecture notes for 02/27/14

Lecture notes for 03/04/14

Lecture notes for 03/06/14

Additional reading materials:

M. Yilmaz, K. Chakrabarty and M. Tehranipoor, Test-pattern selection for screening small-delay defects in very-deep submicron integrated circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 760-773, May 2010.

M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Interconnect-aware and layout-oriented test-pattern selection for small-delay defects", Proc. IEEE International Test Conference, 2008.

Lecture notes for 03/25/14 and 03/27/14

Please download and read these papers:
  1. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, pp. 213-230, April 2002.
  2. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test access mechanism optimization, test scheduling and tester data volume reduction for system-on-chip", IEEE Transactions on Computers, vol. 52, pp. 1619-1632, December 2003.
  3. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Recent advances in TAM optimization, test scheduling, and test resource management for modular testing of core-based SOCs" (invited paper), Proc. IEEE Asian Test Symposium, pp. 320-325, 2002.
  4. A. Sehgal, V. Iyengar and K. Chakrabarty, "SOC test planning using virtual test access architectures", IEEE Transactions on VLSI Systems, vol. 12, pp. 1263-1276, December 2004.
  5. A. Sehgal and K. Chakrabarty, "Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs", Proc. IEEE International Conference on Computer-Aided Design, pp. 88-93, 2005.
Lecture notes for 04/01/14 and 04/03/14

Supplementary Reading Materials (Please download these papers and read them):
  1. N. A. Touba, "Survey of Test Vector Compression Techniques", IEEE Design & Test of Computers, vol. 23, pp. 294-303, July 2006.
  2. Z. Wang and K. Chakrabarty, "Test data compression using selective encoding of scan slices", IEEE Transactions on VLSI Systems, vol. 16, pp. 1429-1440, November 2008.
  3. L. Li and K. Chakrabarty, "Test set embedding for deterministic BIST using a reconfigurable interconnection network, IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems, vol. 23, pp. 1289-1305, September 2004.

Lecture notes for 04/10/14

Supplementary Reading Materials (Please download these papers and read them):
  • H.-H. Lee and K. Chakrabarty, ""Test challenges for 3D integrated circuits", IEEE Design & Test of Computers, vol. 26, pp. 26-35, September/October 2009.
  • E. J. Marinissen and Y. Zorian, "Testing 3D Chips Containing Through-Silicon Vias", Proc. IEEE International Test Conference, 2009.
  • B. Noia and K. Chakrabarty, "Pre-Bond Probing of TSVs in 3D Stacked ICs", Proc. IEEE International Test Conference, 2011.
  • B. Noia, K. Chakrabarty, S. K. Goel, E. J. Marinissen and J. Verbree, "Test-Architecture Optimization and Test Schedulingfor TSV-Based 3-D Stacked ICs", IEEE Transactions on CAD, vol. 30, pp. 1705-1718, November 2011.

    Krishnendu Chakrabarty
    Last updated: Wednesday April 9, 2014