Instructor: Prof. Krish Chakrabarty
Office: 2513 CIEMAS
Office Hours: Tues, Thurs 10-11 AM, or by appointment
Class hours and classroom: Tues, Thurs 8:30-9:45 AM, Room: 115A Hudson Hall
CAD Tools Administrator: Adam Jacovitz
Google group: ECE261_Fall2011
Textbook: N. Weste and D. Harris, CMOS VLSI Design (A Circuits and Systems
Perspective)", 4th edition, Addison-Wesley, 2011.
Prerequisites: Logic Design Fundamentals (ECE 52), Basic Electronics (ECE 163). Students are expected to know logic design, and elementary circuits and device physics from sophomore and junior-level courses. Some background in computer organization is helpful but not required.
Please refer to this PDF file for information about lecture schedule
Course Objectives: To introduce students to CMOS VLSI design methodologies with emphasis on full-custom chip design. Students will make extensive use of CAD tools for IC design, simulation, and layout verification. Specific techniques for designing high-speed, low-power, and easily-testable circuits will also be covered.
Term Project: This is a project-oriented course in which
groups of four students will design and simulate a simple custom IC. The
project will be carried out using Mentor
Graphics CAD tools. Four lead-in lab assignments will allow the students to
gain familiarity with the tools as they proceed with the project. There will be
several checkpoints during the semester to verify the progress made in the
project. Meeting and passing these checkpoints is crucial in order to
successfully complete the chip design. A written project report and a formal
project presentation will also be required.
Members of a team will usually receive the same grade for their project design.
Credit will be given for soundness of engineering design (appropriate
design trade-offs) and ingenuity at all levels of design activity. (Note that
ingenuity is often seen in simplicity, rather than added complexity).
Documentation is equally important. The final report should include an
application-based specification, and a clear description of the resulting
chip implementation. Writing style, figure quality and spelling will count.
Finally, producability is important-this involves completion of the
project so that it is ready to submit for fabrication, simulation and
verification at a level which will assure working parts, and testability of
Homeworks and Exams: There will four evenly-spaced homeworks in the form of problem sets. These will be based on the lecture material. Three in-class exams, tentatively scheduled for October 6, November 8, and December 6, will test basic understanding of the concepts presented in class.
Grading Policy: Four homeworks-10%, Exams-40%, Four labs-20%, Project-30%.
The labs will be simple design exercises aimed at building familiarity and expertise with the Mentor Graphics tools. Note that there will be a penalty of 10% per day on late homework and lab submissions. Late homework and lab submissions will not be accepted after three days. Please do not try these excuses !
For the purposes of establishing standards for submitted graded
work, each student should include the following signed
statement in each piece of work submitted:
"I have adhered to the Duke Community Standard in completing this assignment."