ECE 261: CMOS VLSI Design Methodologies, Fall 2011


Instructor: Prof. Krish Chakrabarty
Office: 2513 CIEMAS
Ph: 660-5244
E-mail: krish@ee.duke.edu
Office Hours: Tues, Thurs 10-11 AM, or by appointment

Class hours and classroom: Tues, Thurs 8:30-9:45 AM, Room: 115A Hudson Hall

Course TAs:

Lab Consultants:

CAD Tools Administrator: Adam Jacovitz
E-mail: cadadmin@ee.duke.edu

Google group: ECE261_Fall2011

Textbook: N. Weste and D. Harris, CMOS VLSI Design (A Circuits and Systems Perspective)", 4th edition, Addison-Wesley, 2011.

Prerequisites: Logic Design Fundamentals (ECE 52), Basic Electronics (ECE 163). Students are expected to know logic design, and elementary circuits and device physics from sophomore and junior-level courses. Some background in computer organization is helpful but not required.

Please refer to this PDF file for information about lecture schedule

Course Objectives: To introduce students to CMOS VLSI design methodologies with emphasis on full-custom chip design. Students will make extensive use of CAD tools for IC design, simulation, and layout verification. Specific techniques for designing high-speed, low-power, and easily-testable circuits will also be covered.

Term Project: This is a project-oriented course in which groups of four students will design and simulate a simple custom IC. The project will be carried out using Mentor Graphics CAD tools. Four lead-in lab assignments will allow the students to gain familiarity with the tools as they proceed with the project. There will be several checkpoints during the semester to verify the progress made in the project. Meeting and passing these checkpoints is crucial in order to successfully complete the chip design. A written project report and a formal project presentation will also be required.

Members of a team will usually receive the same grade for their project design. Credit will be given for soundness of engineering design (appropriate design trade-offs) and ingenuity at all levels of design activity. (Note that ingenuity is often seen in simplicity, rather than added complexity). Documentation is equally important. The final report should include an application-based specification, and a clear description of the resulting chip implementation. Writing style, figure quality and spelling will count. Finally, producability is important-this involves completion of the project so that it is ready to submit for fabrication, simulation and verification at a level which will assure working parts, and testability of the chip.

Homeworks and Exams: There will four evenly-spaced homeworks in the form of problem sets. These will be based on the lecture material. Three in-class exams, tentatively scheduled for October 6, November 8, and December 6, will test basic understanding of the concepts presented in class.

Grading Policy: Four homeworks-10%, Exams-40%, Four labs-20%, Project-30%.

The labs will be simple design exercises aimed at building familiarity and expertise with the Mentor Graphics tools. Note that there will be a penalty of 10% per day on late homework and lab submissions. Late homework and lab submissions will not be accepted after three days. Please do not try these excuses !

For the purposes of establishing standards for submitted graded work, each student should include the following signed statement in each piece of work submitted:
"I have adhered to the Duke Community Standard in completing this assignment."

For more information about the Mentor Graphics tools, please refer to the following:

Introduction to Mentor Graphics Design Tools

Inverter Design: Schematics (pdf file)

Inverter Design: Layout (pdf file)

Please follow these design rules

To use Mentor Graphics tools remotely, please read the instructions on the following Wiki:

Mentor Fonts

Important Announcements

Project Announcement

Lab Assignments

Homeworks

Here are the copies of slides used in class (PDF format):

Lecture notes for 08/30/11

Lecture notes for 09/01/11

Lecture notes for 09/06/11 and 09/08/11

Lecture notes for 09/16/11 (Make-up class)

More on MOS transistor theory, 09/16/11

Lecture notes for 09/16/11 and 09/27/11

Lecture notes for 09/29/11

Lecture notes for 10/04/11 and 10/06/11

Lecture notes for 10/18/11, 10/20/11

No lecture on Tuesday Oct 25

Lecture notes for 10/27/11

Lecture notes for 11/01/11

Lecture notes for 11/03/11

Lecture notes for make-up class on 11/04/11 (4-5:15 pm, 201 HH) and 11/15/11 (regular class)

November 8: Exam II

November 10: No class

Lecture notes for 11/15/11 and 11/17/11

Lecture notes for 11/22/11

Lecture notes for 11/29/11

Lecture notes for 12/01/11


Krishnendu Chakrabarty
Last updated: Wednesday November 30, 2011