PUBLICATIONS

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1. T. Zhang, K. Chakrabarty and R. B. Fair, "Microelectrofluidic Systems: Modeling and Simulation", CRC Press, Boca Raton, FL, 2002.
2. K. Chakrabarty, V. Iyengar and A. Chandra, "Test Resource Partitioning for System-on-a-Chip", Kluwer Academic Publishers, Norwell, MA, 2002.
3. K. Chakrabarty, ed., "SOC (System-on-a-Chip) Testing for Plug and Play Test Automation", Kluwer Academic Publishers, Norwell, MA, 2002.
4. K. Chakrabarty and S. S. Iyengar, "Scalable Infrastructure for Distributed Sensor Networks", Springer, 2005.
5. K. Chakrabarty and F. Su, "Digital Microfluidic Biochips: Synthesis, Testing, and Reconfiguration Techniques", CRC Press, Boca Raton, FL, 2006.
6. K. Chakrabarty and J. Zeng, ed., "Design Automation Methods and Tools for Microfluidics-Based Biochips", Springer, Dordrecht, The Netherlands, 2006.
7. P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Adaptive Cooling of Integrated Circuits using Digital Microfluidics", Artech House, Norwood, MA, 2007.
8. S. Bahukudumbi and K. Chakrabarty, "Wafer-Level Testing and Test During Burn-In for Integrated Circuits", Artech House, Norwell, MA, 2010.
9. K. Chakrabarty and T. Xu, "Digital Microfluidic Biochips: Design and Optimization", CRC Press, Boca Raton, FL, 2010.
10. A. Banerjee and K. Chakrabarty, Test Infrastructure Design for Digital, Mixed-Signal and Hierarchical SOCs, LAP Lambert Academic Publishing, Saarbruecken, Germany, 2011.
11. M. Tehranipoor, K. Peng, and K. Chakrabarty, Testing and Diagnosis for Small-Delay Defects, Springer, 2011.
12. Y. Zhao and K. Chakrabarty, Design and Testing of Digital Microfluidic Biochips, Springer, 2013.
13. S. K. Goel and K. Chakrabarty, ed., Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits, CRC Press, Boca Raton, FL, 2013.
14. P. P. Pande, A. Ganguly and K. Chakrabarty, ed., Design Technologies for Green and Sustainable Computing Systems, Springer, 2013.
15. B. Noia and K. Chakrabarty, Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs, Springer, 2014.
16. Y. Luo, K. Chakrabarty and T.-Y. Ho, Hardware/Software Co-Design and Optimization for Cyberphysical Integration in Digital Microfluidic Biochips, Springer, 2014.
17. Q. Duan, K. Chakrabarty and J. Zeng, Data-Driven Optimization and Knowledge Discovery for an Enterprise Information System, Springer, 2015.
18. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, Knowledge-Driven Board-Level Functional Fault Diagnosis, Springer, 2016.

1. K. Chakrabarty, M. G. Karpovsky and L. B. Levitin, "Fault isolation and diagnosis in multiprocessor systems with point-to-point connections", In Fault-Tolerant Parallel and Distributed Systems, D. R. Avresky and D. R. Kaeli, (eds.), pp. 285-301, Kluwer Academic Publishers, Norwell, MA, 1998.
2. Y. Zhang and K. Chakrabarty, "Adaptive checkpointing with dynamic voltage scaling in embedded real-time systems", In Embedded Software for SoC , A. Jerraya, S. Yoo, N. Wehn and D. Verkest (eds.), Chapter 33, pp. 449-463, Kluwer Academic Publishers, Norwell, MA, 2003.
3. V. Swaminathan, Y. Zou and K. Chakrabarty, "Dynamic power management in wireless sensor networks", In Handbook of Sensor Networks, M. Ilyas and I. Mahgoub (eds.), pp. 29-1--29.34, CRC Press, 2004.
4. V. Swaminathan and K. Chakrabarty, "Operating system power management", In Distributed Sensor Networks, R. R. Brooks and S. S. Iyengar (eds.), pp. 667-696, CRC Press, 2004.
5. Y. Zou and K. Chakrabarty, "Coverage-driven sensor deployment", In Distributed Sensor Networks, R. R. Brooks and S. S. Iyengar (eds.), pp. 453-482, CRC Press, 2004.
6. T. Zhang, K. Chakrabarty and R. B. Fair, "A Hierarchical Design Platform for Microelectrofluidic Systems (MEFS)", In MEMS/NEMS Handbook: Techniques and Applications, C. T. Leondes (ed.), Springer, Chapter 7, pp. 197--234, 2006.
7. Y. Zou and K. Chakrabarty, "Advances in Target Tracking and Active Surveillance using Wireless Sensor Networks", In The Handbook of Algorithmic and Theoretical Aspects of Ad Hoc, Sensor, and Peer-to-Peer Networks, J. Wu (ed.), Chapter 29, pp. 475--489, CRC Press, 2005.
8. H. Sabbineni and K. Chakrabarty, "SCARE: A Scalable Self-Configuration and Adaptive Reconfiguration Scheme for Dense Sensor Networks", In S. Phoha, T. F. La Porta and C. Griffin, ed., Sensor Network Operations, IEEE Press, pp. 14-35, pp. 14-35, 2006.
9. K. Chakrabarty, "Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits", In R. Zurawski, ed., The Embedded Systems Handbook, pp. 27-2--27-27, CRC Press, 2006.
10. K. Chakrabarty, "Efficient Modular Testing and Test Resource Partitioning for Core-Based SOCs", In B. M. Al-Hashimi, ed., SOC: Next Generation Electronics, pp. 751-790, IEE Press, 2006.
11. F. Su, K. Chakrabarty and R. B. Fair, "Microfluidics-based biochips: Technology issues, implementation platforms, and design automation challenges", In K. Chakrabarty and J. Zeng, ed., Design Automation Methods and Tools for Microfluidics-Based Biochips, Springer, 2006.
12. C. Liu, K. Chakrabarty and W.-B. Jone, "System/Network-on-Chip Test Architectures", In L.-T. Wang, C. Stround and N. A. Touba, ed., System-on-Chip Test Architectures: Nanometer Design for Testability, Elsevier, 2007.
13. F. Su, S. Ozev and K. Chakrabarty, "Test Planning and Test Resource Optimization for Droplet-Based Microfluidic Systems", In M. Tehranipoor, ed., Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, Springer, 2007.
14. F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, "Testing and Diagnosis of Realistic Defects in Digital Microfluidic Biochips", In M. Tehranipoor, ed., Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, Springer, 2007.
15. Z. Wang and K. Chakrabarty, "Built-In Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics", In M. Tehranipoor, ed., Emerging Nanotechnologies: Test, Defect Tolerance, and Reliability, Springer, 2007.
16. S. K. Goel and K. Chakrabary, "Power-Aware BIST and Test Data Compression", In P. Girard, N. Nicolici and X. Wen, ed., Power-Aware Testing and Test Strategies for Low Power Devices, pp. 147-174, Springer, 2010.
17. A. Larsson, U. Ingelsson, E. Larsson and K. Chakrabarty, "Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs", In R. Ubar, J. Raik, H. T. Vierhaus, ed., Design and Test Technology for Dependable Systems-on-Chip, IGI Global, 2010.
18. K. Chakrabarty and Y. Zhao, "Digital Microfluidic Biochips: A Vision for Functional Diversity and More than Moore", In N. Voros, A. Mukherjee, N. Sklavos, K. Masselos and M. Huebner, ed., Very Large Scale Integration Systems: Emerging Trends & Challenges, Springer, pp. 263-385, 2011.
19. Y. Zhao, K. Chakrabarty and T. Xu, "Error-Tolerant Digital Microfluidic Lab-on-Chip", In W. A. Goddard III, D. Brenner, G. J. Iafrate and S. E. Lyshevski, ed., Handbook of Nanoscience, Engineering, and Technology (Third Edition), pp. 867-892, CRC Press, 2012.
20. Y. Zou and K. Chakrabarty, "Mobility Management With Integrated Coverage and Connectivity", In H. B. Ammari, ed., The Art of Wireless Sensor Networks, Springer, 2012 (to be published).
21. T. Zhou, R. Roy Choudhury, P. Ning and K. Chakrabarty, "Detecting Sybil Attacks in Vehicular Ad Hoc Networks", In S. S. Iyengar and R. R. Brooks, ed., Distributed Sensor Networks, 2nd ed., Taylor and Francis, Boca Raton, FL, October 2012 (to be published).
22. K. Chakrabarty, Y. Luo and K. Hu "Adaptive and Reconfiguration-Based Error Recovery in Cyberphysical Biochips", In K. Iniewski and S. Carrara, ed., Handbook of Bioelectronics: Directly Interfacing Electronics and Biological Systems, Cambridge University Press, 2013 (to be published).
23. Y. Zhao and K. Chakrabarty, "Microfluidic Logic Gates", In D. Li, editor-in-chief, Encyclopedia of Microfluidics and Nanofluidics, 2nd ed., Springer 2013.
24. R. Shafik, B. N. Al-Hashimi and K. Chakrabarty, "System-level Design Methdology", In J. Mathew, R. Shafik and D. K. Pradhan, ed., Energy Efficient Fault Tolerant Systems, Springer 2013 (to be published).

1993-1997

1. K. Chakrabarty and J. P. Hayes, "Cumulative balance testing of logic circuits", IEEE Transactions on VLSI Systems, pp. 72-83, vol. 3, March 1995.
2. K. Chakrabarty and J. P. Hayes, "Balance testing and balance-testable design of logic circuits", Journal of Electronic Testing: Theory and Applications, vol. 8, pp. 71-86, May 1996.
3. K. Chakrabarty and J. P. Hayes, "Test response compaction using multiplexed parity trees", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 15, pp. 1399-1408, November 1996.
4. K. Chakrabarty and J. P. Hayes, "On the quality of accumulator-based compaction of test responses", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 16, pp. 916-922, August 1997.
5. V. Iyengar and K. Chakrabarty, ``An efficient finite-state machine implementation of Huffman decoders'', Information Processing Letters, vol. 64, pp. 271-275, December 1997.

   1998

6. M. G. Karpovsky, K. Chakrabarty and L. B. Levitin, "On a new class of codes for covering vertices in graphs", IEEE Transactions on Information Theory, vol. 44, pp. 599-611, March 1998.
7. K. Chakrabarty and J. P. Hayes, ``Balanced boolean functions'', IEE Proceedings: Computers and Digital Techniques, vol. 145, pp. 52-62, January 1998.
8. K. Chakrabarty, "Zero-aliasing space compaction using linear compactors with bounded overhead", IEEE Transactions on CAD/ICAS, vol. 17, pp. 452-457, May 1998.
9. V. Iyengar, K. Chakrabarty and B. T. Murray, ``Huffman encoding of test sets for sequential circuits'', IEEE Transactions on Instrumentation and Measurement, vol. 47, pp. 21-25, February 1998.
10. K. Chakrabarty and J. P. Hayes, "Zero-aliasing space compaction using multiple parity signatures", IEEE Transactions on VLSI Systems, vol. 6, pp. 309-313, June 1998.
11. K. Chakrabarty and B. T. Murray, "Design of built-in test generator circuits using width compression", IEEE Transactions on CAD/ICAS, vol. 17, pp. 1044-1051, October 1998.
12. K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal zero-aliasing space compaction of test responses", IEEE Transactions on Computers, vol. 47, pp. 1171-1187, November 1998.

    1999

13. M. G. Karpovsky, K. Chakrabarty, L. B. Levitin and D. R. Avresky, "On the covering of vertices for fault diagnosis in hypercubes", Information Processing Letters, vol. 69, pp. 99-103, January 1999.
14. V. Iyengar, K. Chakrabarty and B. T. Murray, "Deterministic built-in pattern generation for sequential circuits", Journal of Electronic Testing: Theory and Applications, vol. 15, pp. 97-114, August/October, 1999.

    2000

15. K. Chakrabarty and S. R. Das, "Test set embedding based on width compression for mixed-mode BIST", IEEE Transactions on Instrumentation and Measurement, vol. 49, pp. 671-678, June 2000.
16. S. R. Das, T. F. Barakat, E. M. Petriu, M. H. Assaf and K. Chakrabarty, "Space compression revisited", IEEE Transactions on Instrumentation and Measurement, vol. 49, pp. 690-705, June 2000.
17. K. Chakrabarty, "Test scheduling for core-based systems using mixed-integer linear programming", IEEE Transactions on CAD/ICAS, vol. 19, pp. 1163-1174, October 2000.
18. K. Chakrabarty, B. T. Murray and V. Iyengar, "Deterministic built-in pattern generation for high-performance circuits using twisted ring counters", IEEE Transactions on VLSI Systems, vol. 8, pp. 633-636, October 2000.

    2001

19. K. Chakrabarty, "Optimal test access architectures for system-on-a-chip", ACM Transactions on Design Automation of Electronic Systems, vol. 6, pp. 26-49, January 2001.
20. A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures based on Golomb codes", IEEE Transactions on CAD/ICAS, vol. 20, pp. 355-368, March 2001.
21. T. Zhang, F. Cao, A. Dewey, R. B. Fair and K. Chakrabarty, "Performance analysis of microelectrofluidic systems using hierarchical modeling and simulation", IEEE Transactions on Circuits and Systems (Part II: Analog and Digital Signal Processing), vol. 48, pp. 482-491, May 2001.
22. V. Iyengar, H. Date, M. Sugihara and K. Chakrabarty, "Hierarchical intellectual property protection using partially-mergeable cores", IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences: Special Section on VLSI Design and CAD Algorithms, pp. 2632-2638, November 2001.
23. H. Qi, S. S. Iyengar and K. Chakrabarty, "Distributed sensor fusion--a review of recent research", Journal of the Franklin Institute, vol. 338, pp. 655-668, September 2001.
24. V. Swaminathan and K. Chakrabarty, "Real-time task scheduling for energy-aware embedded systems", Journal of the Franklin Institute, vol. 338, pp. 729-750, September 2001.
25. H. Qi, S. S. Iyengar and K. Chakrabarty, "Multi-resolution data integration using mobile agents in distributed sensor networks", IEEE Transactions on Systems, Man and Cybernetics (Part C), vol. 31, pp. 383-391, August 2001.
26. A. Chandra, K. Chakrabarty and M. C. Hansen, "Efficient test application for core-based systems using twisted-ring counters", VLSI Design, vol. 12, pp. 475-486, December 2001.
27. A. Chandra and K. Chakrabarty, "Test resource partitioning for system-on-a-chip based on test data compression and on-chip decompression", IEEE Design and Test of Computers, vol. 18, pp. 80-91, September/October, 2001.
28. S. Swaminathan and K. Chakrabarty, "On using twisted-ring counters for test set embedding in BIST", Journal of Electronic Testing: Theory and Applications, vol. 17, pp. 530-542, December 2001.
29. J. Ding, K. Chakrabarty and R. B. Fair, "Scheduling of microfluidic operations for reconfigurable two-dimensional electrowetting arrays", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 20, pp. 1463-1468, December 2001.

    2002

30. H. Qi, X. Wang, S. S. Iyengar and K. Chakrabarty, "High performance sensor data integration in distributed sensor networks using mobile agents", International Journal of High Performance Computing Applications, volume 16, no. 3, pp. 325-335, 2002.
31. V. Iyengar and K. Chakrabarty, ""Test bus sizing for system-on-a-chip", IEEE Transactions on Computers, vol. 51, pp. 449-459, May 2002.
32. T. Zhang, K. Chakrabarty and R. B. Fair, "Integrated hierarchical design of microelectrofluidic systems using SystemC", Microelectronics Journal, vol. 33, pp. 459-470, May 2002.
33. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test wrapper and test access mechanism co-optimization for system-on-a-chip", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 18, pp. 213-230, April 2002.
34. A. Chandra and K. Chakrabarty, "Low-power scan testing and test data compression for system-on-a-chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 597-604, May 2002.
35. K. Chakrabarty, S. S. Iyengar, H. Qi and E. Cho, "Grid coverage for surveillance and target location in distributed sensor networks", IEEE Transactions on Computers, vol. 51, pp. 1448-1453, December 2002.
36. A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression based on internal scan chains and Golomb coding", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 715-722, June 2002.
37. T. Zhang, K. Chakrabarty and R. B. Fair, "Design of reconfigurable composite microsystems using hardware/software co-design principles", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 987-995, August 2002.
38. B. B. Bhattacharya, A. Dmitriev, M. Goessel and K. Chakrabarty, "Synthesis of single-output space compactor for scan-based sequential circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 1171-1179, October 2002.
39. V. Iyengar and K. Chakrabarty, "System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 1088-1094, September 2002.
40. S. R. Das, J. Y. Liang, E. M. Petriu, M. H. Assaf, W.-B. Jone and K. Chakrabarty, "Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering", IEEE Transactions on Instrumentation and Measurement, vol. 51, pp. 150-172, February 2002.

    2003

41. A. Chandra and K. Chakrabarty, ""Test data compression and test resource partitioning for system-on-a-chip using frequency-directed run-length (FDR) codes", IEEE Transactions on Computers, vol. 52, pp. 1076-1088, August 2003.
42. K. Chakrabarty, "A synthesis-for-transparency approach for hierarchical and system-on-a-chip test", IEEE Transactions on VLSI Systems, vol. 11, pp. 167-179, April 2003.
43. A. Chandra and K. Chakrabarty, "A unified approach to reduce SOC test data volume, scan power and testing time", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 352-362, March 2003.
44. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Efficient test access mechanism optimization for system-on-chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 635-643, May 2003.
45. C. Liu and K. Chakrabarty, ""Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 593-604, May 2003.
46. V. Swaminathan and K. Chakrabarty, "Energy-conscious, deterministic I/O device scheduling in hard real-time systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 847-858, July 2003.
47. Y. Zou and K. Chakrabarty, "Target localization based on energy considerations in distributed sensor networks", Ad Hoc Networks, vol. 1, pp. 261-272, 2003.
48. K. Chakrabarty and M. Seuring, "Space compaction of test responses using orthogonal transmission functions", IEEE Transactions on Instrumentation and Measurement, vol. 52, pp. 1353-1362, October 2003.
49. S. R. Das, M. Sudama, M. H. Assaf, E. M. Petriu, W.-B. Jone, K. Chakrabarty and M. Sahinoglu, "Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets", IEEE Transactions on Instrumentation and Measurement, vol. 52, pp. 1363-1380, October 2003.
50. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test access mechanism optimization, test scheduling and tester data volume reduction for system-on-chip", IEEE Transactions on Computers, vol. 52, pp. 1619-1632, December 2003.
51. L. Li, K. Chakrabarty and N. A. Touba, "Test data compression using dictionaries with selective entries and fixed-length indices", ACM Transactions on Design Automation of Electronic Systems, vol. 8, pp. 470-490, October 2003.

    2004

52. Y. Zou and K. Chakrabarty, "Sensor deployment and target localization in distributed sensor networks", ACM Transactions on Embedded Computing Systems, vol. 3, pp. 61-91, February 2004.
53. Y. Zhang and K. Chakrabarty, "Dynamic adaptation for fault tolerance and power management in embedded real-time systems", ACM Transactions on Embedded Computing Systems, vol. 3, pp. 336-360, May 2004.
54. T. Zhang, K. Chakrabarty and R. B. Fair, "Behavioral modeling and performance evaluation of microelectrofluidics-based PCR systems using SystemC", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 23, pp. 843-858, June 2004.
55. Y. Zou and K. Chakrabarty, "Uncertainty-aware and coverage-oriented deployment for sensor networks", Journal of Parallel and Distributed Computing, vol. 64, pp. 788-798, July 2004.
56. A. Chandra and K. Chakrabarty, "Analysis of test application time for test data compression methods based on compression codes", Journal of Electronic Testing: Theory and Applications, vol. 20, pp. 199-212, April 2004.
57. Q. Wu, N. S. V. Rao, J. Barhen, S. S. Iyengar, V. K. Vaishnavi, H. Qi and K. Chakrabarty, "On computing mobile agent routes for data fusion in distributed sensor networks", IEEE Transactions on Knowledge and Data Engineering, vol. 16, pp. 740-753, June 2004.
58. C. Liu and K. Chakrabarty, "Compact dictionaries for fault diagnosis in scan-BIST", IEEE Transactions on Computers, vol. 53, pp. 775-780, June 2004.
59. L. Li and K. Chakrabarty, "Test set embedding for deterministic BIST using a reconfigurable interconnection network", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 23, pp. 1289-1305, September 2004.
60. V. Swaminathan and K. Chakrabarty, "Network flow techniques for dynamic voltage scaling in hard real-time systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 23, pp. 1385-1398, October 2004.
61. M. Goessel, K. Chakrabarty, V. Ocheretnij and A. Leininger, "Identification of failing vectors using signature analysis with application to scan-BIST", Journal of Electronic Testing: Theory and Applications, vol. 20, pp. 611-622, December 2004.
62. C. Liu and K. Chakrabarty, "Identification of error-capturing scan cells in scan-BIST with applications to system-on-chip", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 23, pp. 1447-14459, October 2004.
63. A. Sehgal, V. Iyengar and K. Chakrabarty, "SOC test planning using virtual test access architectures", IEEE Transactions on VLSI Systems, vol. 12, pp. 1263-1276, December 2004.
64. L. Li and K. Chakrabarty, "On using exponential-Golomb codes and subexponential codes for system-on-a-chip test data compression", Journal of Electronic Testing: Theory and Applications, vol. 20, pp. 677-670, December 2004.
65. H. Sabbineni and K. Chakrabarty, "A survey of energy-efficient self-organization and data dissemination protocols for ad hoc sensor networks", Sensor Letters, vol. 2, pp. 194-204, September/December 2004.

    2005

66. V. Swaminathan and K. Chakrabarty, "Pruning-based, energy-optimal, deterministic I/O device scheduling for hard real-time systems", ACM Transactions on Embedded Computing Systems, vol. 4, pp. 141-167, February 2005.
67. K. Chakrabarty, V. Iyengar and M. Krasniewski, "Test planning for modular testing of hierarchical SOCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 24, pp. 435-448, March 2005.
68. F. Su, S. Ozev and K. Chakrabarty, "Ensuring the operational health of droplet-based microelectrofluidic biosensor systems", IEEE Sensors, vol. 5, pp. 763-773, August 2005.
69. H. Sabbineni and K. Chakrabarty, "Location-aided flooding: An energy-efficient data dissemination protocol for wireless sensor networks", IEEE Transactions on Computers, vol. 54, pp. 36-46, January 2005.
70. K. Chakrabarty, "Low-cost modular testing and test resource partitioning for SOCs" (invited paper), IEE Proceedings: Computers and Digital Techniques, vol. 152 pp. 427-441, May 2005.
71. H. M. F. AboElFotoh, S. S. Iyengar and K. Chakrabarty, "Computing reliability and message delay for cooperative wireless distributed sensor networks subject to random failures", IEEE Transactions on Reliability, vol. 54, pp. 145-155, 2005.
72. A. Sehgal, A. Dubey, E. J. Marinissen, C. Wouters, H. Vranken and K. Chakrabarty, "Redundancy modeling and array yield analysis for repairable embedded memories", IEE Proceedings: Computers and Digital Techniques, vol. 152, pp. 97-106, January 2005.
73. M. Tehranipoor, M. Nourani and K. Chakrabarty, "Nine-coded compression technique for testing embedded cores in SoCs", IEEE Transactions on VLSI Systems, vol. 13, pp. 719-731, June 2005.
74. Y. Zou and K. Chakrabarty, "A distributed coverage- and connectivity-centric technique for selecting active nodes in wireless sensor networks", IEEE Transactions on Computers, vol. 54, pp. 978-991, August 2005.
75. C. Liu and K. Chakrabarty, "Design and analysis of compact dictionaries for diagnosis in scan-BIST", IEEE Transactions on VLSI Systems, vol. 13, pp. 979-984, August 2005.
76. L. Li, K. Chakrabarty, S. Kajihara and S. Swaminathan, "A three-stage compression approach to reduce test data volume and testing time for IP cores in SOCs", IEE Proceedings: Computers and Digital Techniques, vol. 152, pp. 704-712, November 2005.
77. K. Chakrabarty and J. Zeng, "Design automation for microfluidics-based biochips", ACM Journal on Emerging Technologies in Computing Systems, vol. 1, pp. 186-223, December 2005.

    2006

78. Y. Zhang and K. Chakrabarty, "A unified approach for fault tolerance and dynamic power management in real-time embedded systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 111-125, January 2006.
79. F. Su, K. Chakrabarty and R. B. Fair, "Microfluidics-based biochips: technology issues, implementation platforms, and design automation challenges", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 211-223, February 2006.
80. F. Su, S. Ozev and K. Chakrabarty, "Concurrent testing of digital microfluidics-based biochips", ACM Transactions on Design Automation of Electronic Systems, vol 11, pp. 442-464, April 2006.
81. P. Rosinger, B. M. Al-Hashimi and K. Chakrabarty, "Thermal-safe test scheduling for core-based system-on-chip integrated circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 2502-2512, November 2006.
82. A. Sehgal, S. Ozev and K. Chakrabarty, " Test infrastructure design for mixed-signal SOCs with wrapped analog cores", IEEE Transactions on VLSI Systems, vol. 14, pp. 292-304, March 2006.
83. F. Su, S. Ozev and K. Chakrabarty, "Test planning and test resource optimization for droplet-based microfluidic systems", Journal of Electronic Testing: Theory and Applications, vol. 22, pp. 199-210, April 2006.
84. F. Su and K. Chakrabarty, "Defect tolerance based on graceful degradation and dynamic reconfiguration for digital microfluidics-based biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 2944-2953, December 2006.
    (Received IEEE Circuits and Systems Society Outstanding Young Author Award, 2008)
85. F. Su and K. Chakrabarty, "Module placement for fault-tolerant microfluidics-based biochips", ACM Transactions on Design Automation of Electronic Systems, vol. 11, pp. 682-710, 2006.
86. F. Su and K. Chakrabarty, "Yield enhancement of reconfigurable microfluidics-based biochips using interstitial redundancy", ACM Journal on Emerging Technologies in Computing Systems, vol. 2, pp. 104-128, April 2006.
87. A. Wuertemberber, P. Rosinger, B. Al-Hashimi and K. Chakrabarty, "Cost model-driven test resource partitioning for SoCs", IEE Electronics Letters, pp. 915-916, August 3, 2006.

    2007

88. A. Sehgal and K. Chakrabarty, "Optimization of dual-speed TAM architectures for efficient modular testing of SOCs", IEEE Transactions on Computers, vol. 56, pp. 120-133, January 2007.
89. L. Li, Z. Wang and K. Chakrabarty, "Scan-BIST based on cluster analysis and the encoding of repeating sequences", ACM Transactions on Design Automation of Electronic Systems, vol. 12, DOI Bookmark: 10.1145/1188275.1188279, January 2007 (Article 4).
90. Z. Wang and K. Chakrabarty, "Built-in self-test and defect tolerance in molecular electronics-based nanofabrics", Journal of Electronic Testing: Theory and Applications, vol. 23, pp. 145-161, June 2007.
91. F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, "Testing and diagnosis of realistic defects in digital microfluidic biochips", Journal of Electronic Testing: Theory and Applications, vol. 23, pp. 219-233, June 2007.
92. Y. Zou and K. Chakrabarty, "Redundancy analysis and a distributed self-organization protocol for fault-tolerant wireless sensor networks", International Journal of Distributed Sensor Networks, vol. 3, pp. 243-272, July 2007.
93. Y. Zou and K. Chakrabarty, "Distributed mobility management for target tracking in mobile sensor networks", IEEE Transactions on Mobile Computing, vol. 8, pp. 872-887, August 2007.
94. Q. Xu, N. Nicolici and K. Chakrabarty, "Test wrapper design and optimization under power constraints for embedded cores with multiple clock frequencies", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 26, pp. 1539-1547, August 2007.
95. T. Xu, W. Hwang, F. Su and K. Chakrabarty, "Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints", ACM Journal on Emerging Technologies in Computing Systems, vol. 3, Article 14, November 2007 (DOI 10.1145/1295231.1295235).
96. S. Bahukudumbi and K. Chakrabarty, "Wafer-level modular testing of core-based SOCs", IEEE Transactions on VLSI Systems, vol. 15, pp. 1144-1154, October 2007.
97. T. Xu and K. Chakrabarty, "Parallel scan-like test and multiple-defect diagnosis for digital microfluidic biochips", IEEE Transactions on Biomedical Circuits and Systems, vol. 1, pp. 148-158, June 2007.

    2008

98. F. Su and K. Chakrabarty, "High-level synthesis of digital microfluidic biochips", ACM Journal on Emerging Technologies in Computing Systems, vol. 3, Article 16, January 2008.
99. P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Adaptive cooling of integrated circuits using digital microfluidics", IEEE Transactions on VLSI Systems, vol. 16, pp. 432-443, April 2008.
100. Z. Wang and K. Chakrabarty, "Test-quality/cost optimization using output-deviation-based reordering of test patterns", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 352-365, February 2008.
101. S. Samii, M. Selkala, E. Larsson, K. Chakrabarty and Z. Peng, "Cycle-accurate test power modeling and its application to SoC test architecture design and scheduling", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 25, pp. 973-977, May 2008.
102. N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel, S. Pravossoudovitch and C. Landrault, "A selective scan slice encoding technique for test data volume and test power reduction", Journal of Electronic Testing: Theory and Applications, vol. 24, pp. 353-364, August 2008.
103. Z. Wang and K. Chakrabarty, "Test data compression using selective encoding of scan slices", IEEE Transactions on VLSI Systems, vol. 16, pp. 1429-1440, November 2008.
104. D. Xiang, Y. Zhao, K. Chakrabarty and H. Fujiwara, "A reconfigurable scan architecture with weighted scan-enable signals for deterministic BIST", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 999-1012, June 2008.
105. T. Xu and K. Chakrabarty, "Integrated droplet routing and defect tolerance in the synthesis of digital microfluidic biochips", ACM Journal on Emerging Technologies in Computing Systems, vol. 4., no. 3, Article 11, August 2008.
106. P. Y. Paik, V. K. Pamula and K. Chakrabarty, "A digital microfluidic approach to chip cooling'', IEEE Design & Test of Computers, vol. 25, pp. 372-381, July/August 2008.
107. T. Xu and K. Chakrabarty, "Defect-aware high-level synthesis and module placement for microfluidic biochips", IEEE Transactions on Biomedical Circuits and Systems, vol. 2, pp. 50-62, March 2008.
108. A. Sehgal, S. Bahukudumbi and K. Chakrabarty, "Power-aware SOC test planning for effective utilization of port-scalable testers", ACM Transactions on Design Automation of Electronic Systems, vol. 13, no. 3, Article 53, July 2008.
109. T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara, "Thermal-aware test access mechanism optimization for system-on-chips", IEICE Transactions on Information and Systems, vol. E91-D, pp. 2440--2448, October 2008.
110. T. Xu and K. Chakrabarty, "A droplet-manipulation method for achieving high-throughput in cross-referencing-based digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 1905-1917, November 2008.

     2009

111. S. Bahukudumbi and K. Chakrabarty, "Test-length and TAM optimization for wafer-level reduced pin-count testing of core-based SoCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 111-120, January 2009.
112. Z. Wang, H. Fang, K. Chakrabarty and M. Bienek, "Deviation-based LFSR reseeding for test-data compression", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 259-271, February 2009.
113. S. K. Goel, E. J. Marinissen, A. Sehgal and K. Chakrabarty, "Testing of SOCs with hierarchical cores: Common fallacies, test-access optimization, and test scheduling", IEEE Transactions on Computers, vol. 58, pp. 409-423, March 2009.
114. S. Bahukudumbi, S. Ozev, K. Chakrabarty and V. Iyengar, "Wafer-level defect screening for "big-D/small-A" mixed-signal SoCs", IEEE Transactions on VLSI Systems, vol. 17, pp. 587-592, April 2009.
115. S. Bahukudumbi and K. Chakrabarty, "Power management using test-pattern ordering for wafer-level test-during-burn-in", IEEE Transactions on VLSI Systems, vol. 17, pp. 1730-1741, December 2009.
116. Y. Zhang, Q, Xu and K. Chakrabarty, "SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects", ACM Transactions on Design Automation of Electronic Systems, vol. 14, Article 4, January 2009.
117. X. Wu, P. Falkenstern, K. Chakrabarty and Y. Xie, "Scan-chain design and optimization for three-dimensional integrated circuits", ACM Journal on Emerging Technologies in Computing Systems, vol. 5, Article 9, July 2009.
118. Z. Wang, K. Chakrabarty and S. Wang, "Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 1251-1264, August 2009.
119. Y. Zhao and K. Chakrabarty, "On-line testing of lab-on-chip using reconfigurable digital-microfluidic compactors", International Journal of Parallel Programming, vol. 37, pp. 370-388, August 2009.
120. T. Xu and K. Chakrabarty, "Fault modeling and functional test methods for digital microfluidic biochips", IEEE Transactions for Biomedical Circuits and Systems, vol. 3, pp. 241-253, August 2009.
121. V. Mao, V. Thusu, C. Dwyer and K. Chakrabarty, "Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics", IET Computers and Digital Techniques, vol. 3, pp. 553-569, 2009.
122. H.-H. S. Lee and K. Chakrabarty, ""Test challenges for 3D integrated circuits", IEEE Design & Test of Computers, vol. 26, pp. 26-35, September/October 2009.

     2010

123. H. Sabbineni and K. Chakrabarty, "An energy-efficient data delivery scheme for delay-sensitive traffic in wireless sensor networks", International Journal of Distributed Sensor Networks, vol. 2010, Article ID 792068, DOI: 10.1155/2010/792068, 2010.
124. K. Chakrabarty, "Design automation and test solutions for digital microfluidic biochips" (invited tutorial), IEEE Transactions on Circuits and Systems I, vol, 57, pp. 4-17, January 2010.
125. T. Xu, K. Chakrabarty and V. K. Pamula, "Defect-tolerant design and optimization of a digital microfluidic biochip for protein crystallization", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 552-565, April 2010.
126. H. Fang, K. Chakrabarty and H. Fujiwara, "RTL DFT techniques to enhance defect coverage for functional test sequences", Journal of Electronic Testing: Theory and Applications, vol. 26, pp. 151-164, April 2010.
127. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Test-pattern selection for screening small-delay defects in very-deep submicron integrated circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 760-773, May 2010.
128. Y. Zhao, T. Xu and K. Chakrabarty, "Integrated control-path design and error recovery in digital microfluidic lab-on-chip", ACM Journal on Emerging Technologies in Computing Systems, vol. 3, Article No. 11, August 2010.
129. K. Chakrabarty, R. B. Fair and J. Zeng, "Design tools for digital microfluidic biochips: Towards functional diversification and more than Moore" (Keynote Paper), IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1001-1017, July 2010.
130. S. Khursheed, B. M. Al-Hashimi, K. Chakrabarty and P. Harrod, "Gate-sizing-based single V_DD test for bridge defects in multi-voltage designs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1409-1421, September 2010.
131. Y. Zhao and K. Chakrabarty, "Digital microfluidic logic gates and their application to built-in self-test of lab-on-chip", IEEE Transactions on Biomedical Circuits and Systems, vol. 4, pp. 250-262, August 2010.
132. X. Wu, Y. Chen, K. Chakrabarty and Y. Xie, "Test-access mechanism optimization for core-based three-dimensional SOCs", Microelectronics Journal, vol. 41, pp. 601-615, October 2010.
133. S. Roy, B. B. Bhattacharya and K. Chakrabarty, "Optimization of dilution and mixing of biochemical samples using digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 1696-1708, November 2010.
134. H. Sabbineni and K. Chakrabarty, "Data collection in event-driven wireless sensor networks with mobile sinks", International Journal of Distributed Sensor Networks, vol. 2010, Article ID 402680, DOI: 10.1155/2010/402680, 2010.

     2011

135. B. Noia and K. Chakrabarty, "Test-wrapper optimisation for modular testing of embedded cores in TSV-based three-dimensional SOCs", IET Computers and Digital Techniques, vol. 5, pp. 186-197, May 2011.
136. X. Kavousianos, V. Tenentes, K. Chakrabarty, and M. Kalligeros, "Defect-oriented LFSR seseeding to target unmodeled defects using stuck-at test sets", IEEE Transactions on VLSI Systems, vol. 19, pp. 2330-2335, December 2011.
137. M. Yilmaz, M. Tehranipoor and K. Chakrabarty, "A metric to target small-delay defects in industrial circuits", IEEE Design & Test of Computers, vol. 28, pp. 52-61, March/April 2011.
138. Y. Zhao and K. Chakrabarty, "Fault diagnosis in lab-on-chip using digital microfluidic logic gates", Journal of Electronic Testing: Theory and Applications, vol. 27, pp. 69-83, February 2011.
139. T. Zhou, R. Roy Choudhury, P. Ning and K. Chakrabarty, "P2DAP -- Detecting Sybil attacks in vehicular ad hoc networks"'', IEEE Journal on Selected Areas in Communications (Special Issue on Vehicular Communications and Networks), vol. 29, pp. 582--594, March 2011.
140. X. Kavousianos and K. Chakrabarty, "Generation of compact stuck-at test sets targeting unmodeled defects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 787-791, May 2011.
141. Y. Zhao, T. Xu and K. Chakrabarty, "Broadcast electrode-addressing and scheduling methods for pin-constrained digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 986-999, July 2011.
142. B. Noia, K. Chakrabarty, S. K. Goel, E. J. Marinissen, and J. Verbree, "Test-Architecture Optimization and Test Scheduling for TSV-Based 3D Stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 1705-1718, November 2011.
143. Z. Chen, K. Chakrabarty and D. Xiang, "MVP: Minimum-violations partitioning for reducing capture power in at-speed delay-fault testing", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 30, pp. 1762-1769, November 2011.
144. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty and B. B. Bhattacharya, "Test planning in digital microfluidic biochips using efficient Eulerization techniques", Journal of Electronic Testing: Theory and Applications, vol. 27, pp. 657-671, October 2011.

     2012

145. B. Noia, K. Chakrabarty and E. J. Marinissen, "Optimization methods for post-bond testing of 3D stacked ICs", Journal of Electronic Testing: Theory and Applications, vol. 28, pp. 103-120, February 2012.
146. Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, "Physical-defect modeling and optimization for fault-insertion test", IEEE Transactions on VLSI Systems, vol. 20, pp. 723-736, April 2012.
147. Y. Zhao, K. Chakrabarty, R. Sturmer and V. K. Pamula, "Optimization techniques for the synchronization of concurrent fluidic operations in pin-constrained digital microfluidic biochip", IEEE Transactions on VLSI Systems, vol. 20, pp. 1132-1145, June 2012.
     (Received IEEE Circuits and Systems Society Outstanding Young Author Award, 2013)
148. L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Test-architecture optimization for 3D SOCs under pre-bond test-pin-count constraint", IEEE Transactions on VLSI Systems, vol. 20, pp. 1621-1633, September 2012.
149. S. Roy, D. Mitra, B. B. Bhattacharya and K. Chakrabarty, "Congestion-aware layout design for high-throughput digital microfluidic biochips, ACM Journal on Emerging Technologies in Computing Systems, vol. 8, Article 17, August 2012.
150. H. Fang, K. Chakrabarty, A. Jas, S. Patil and C. Trimurti, "Functional test-sequence grading at register-transfer level", IEEE Transactions on VLSI Systems, vol. 20, pp. 1890-1894, October 2012.
151. Y. Zhao, K. Chakrabarty and B. B. Bhattacharya, "Testing of low-cost digital microfluidic biochips with non-regular array layouts", Journal of Electronic Testing: Theory and Applications, vol. 28, pp. 243-255, April 2012.
152. Y. Zhao and K. Chakrabarty, "Simultaneous optimization of droplet routing and control-pin mapping to electrodes in digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 242-254, February 2012.
153. Y. Zhao and K. Chakrabarty, "Cross-contamination avoidance for droplet routing in digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 817-830, June 2012.
154. H. Fang, K. Chakrabarty, Z. Wang and X. Gu, "Reproduction and detection of board-level functional failures", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 630-643, April 2012.
155. H. Fang, K. Chakrabarty, Z. Wang and X. Gu, "Diagnosis of board-level functional failures under uncertainty using Dempster-Shafer theory", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 1586-1599, October 2012.
156. Y.-L. Hsieh, T-Y. Ho and K. Chakrabarty, "A reagent-saving mixing algorithm for preparing multiple-target biochemical samples using digital microfluidics", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 1656-1669, November 2012.
157. X. Kavousiaonos, K. Chakrabarty, A. Jain and R. Parekhji, "Test schedule optimization for multicore SoCs: Handling dynamic voltage scaling and multiple voltage islands", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, pp. 1754-1766, November 2012.
158. C.-J. Shih, C.-Y. Hsu, C.-Y.Kou, J. Li, J.-C. Rau and K. Chakrabarty, "Thermal-aware test schedule and TAM co-optimization for three dimensional IC", Active and Passive Electronic Components, vol. 2012, Article ID 763572, 2012. DOI:10.1155/2012/763572.

     2013

159. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. Chakrabarty and Y.-H. Hu, "Counter-based output selection for test response compaction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 152-164, January 2013.
160. Y. Luo, K. Chakrabarty and T-Y. Ho, Error recovery in cyberphysical digital-microfluidic biochips, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 59-72, January 2013.
161. B. Noia and K. Chakrabarty, "TSV probing for pre-bond testing of 3D stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 547-558, April 2013.
162. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Board-level functional fault diagnosis using artificial neural networks, support-vector machines, and weighted-majority voting", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 723-736, May 2013.
163. K. Peng, M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Crosstalk- and process variations-aware high-quality tests for small-delay defects", IEEE Transactions on VLSI Systems, vol. 21, pp. 1129-1142, June 2013.
164. F. Bao, K. Peng, M. Yilmaz, K. Chakrabarty, L. Winemberg, and M. Tehranipoor, "Efficient pattern generation for small-delay defects using selection of critical faults", Journal of Electronic Testing: Theory and Applications (JETTA), vol. 29, pp. 35-48, February 2013.
165. D. Xiang, J. Li, K. Chakrabarty and X. Lin, "Test compaction for small delay defects using an effective path selection scheme", ACM Transactions on Design Automation of Electronic Systems, vol. 18, Article no. 44, July 2013.
166. N. Karimi and K. Chakrabarty, "Detection, diagnosis and recovery from clock-domain crossing failures in multi-clock SoCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1395-1408, September 2013.
167. Y. Luo and K. Chakrabarty, "Design of pin-constrained general-purpose digital microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1307-1320, September 2013.
168. F. Bao, K. Peng, M. Tehranipoor and K. Chakrabarty, "Generation of effective 1-detect TDF patterns for detecting small-delay defects", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1583-1594, October 2013.
169. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "A high-throughput dilution engine for sample preparation on digital microfluidic biochips", IET Computers and Digital Techniques, vol. 8, no. 4, pp. 163-171, July 2014.
170. Y. Luo, K. Chakrabarty and T.-Y. Ho, "Real-time error recovery in cyberphysical digital-microfluidic biochips using a compact dictionary", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 32, pp. 1839-1852, December 2013.

     2014

171. Z. Zhang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, "Static power reduction using variation-tolerant and reconfigurable multi-mode power switches", IEEE Transactions on VLSI Systems, vol. 22, pp. 13-26, January 2014.
172. S. Khursheed, K. Shi, B. M. Al-Hashimi, P. R. Wilson and K. Chakrabarty, "Delay test for diagnosis of power switches", IEEE Transactions on VLSI Systems, vol. 22, pp. 197-206, February 2014.
173. C.-Y. Kuo, C.-J. Shih, Y.-C. Lu, J. Li and K. Chakrabarty, "Testing of TSV-induced small delay faults for three dimensional integrated circuits", IEEE Transactions on VLSI Systems, vol. 22, pp. 667-674, March 2014.
174. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Board-level functional fault diagnosis using multi-kernel support vector machines and incremental learning", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 279-290, February 2014.
175. Y.-L. Hsieh, T.-Y. Ho and K. Chakrabarty, "Biochip synthesis and dynamic error recovery for sample preparation using digital microfluidics", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 183-196, February 2014.
176. B. Noia and K. Chakrabarty, "Retiming for delay recovery after DfT insertion on inter-die paths in 3D ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 464-475, March 2014.
177. M. Richter and K. Chakrabarty, "Optimization of test pin-count, test scheduling, and test access for NoC-based multicore SoCs", IEEE Transactions on Computers, vol. 63, pp. 691-702, March 2014.
178. S. Deutsch and K. Chakrabarty, "Contactless pre-bond TSV test and diagnosis using ring oscillators and multiple voltage levels", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 774-785, May 2014.
179. Y. Luo, K. Chakrabarty and T.-Y. Ho, "Biochemistry synthesis on a cyberphysical digital microfluidics platform under completion-time uncertainties in fluidic operations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 903-916, June 2014.
180. M. Agrawal, M. Richter and K. Chakrabarty, "Test-delivery optimization in manycore SOCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1067-1080, July 2014.
181. R. Wang, Z. Zhang, X. Kavousianos, Y. Tsiatouhas and K. Chakrabarty, "Built-in self-test, diagnosis and repair of multi-mode power switches", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1231-1244, August 2014.
182. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Information-theoretic framework for evaluating and guiding board-level functional fault diagnosis", IEEE Design & Test, vol. 31, pp. 65-75, May/June 2014.
183. D. Mitra, S. Roy, S. Bhattacharjee, K. Chakrabarty and B. B. Bhattacharya, "On-chip sample preparation for multiple targets using digital microfluidics", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1131-1144, August 2014.
184. R. Wang, K. Chakrabarty and B. Eklow, "Scan-based testing of post-bond silicon interposer interconnects in 2.5D ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1410-1423, September 2014.
185. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "Theory and analysis of generalized mixing and dilution of biochemical fluids using digital microfluidic biochips", ACM Journal on Emerging Technologies in Computing Systems, vol. 11, September 2014.
186. K. Chakrabarty, M. Agrawal, S. Deutsch, B. Noia, R. Wang and F. Ye, "Test and design-for-testability solutions for 3D integrated circuits" (Invited Paper), Journal of Information Processing (Information Processing Society of Japan), vol. 7, pp. 56-73, August 2014.
187. K. Hu, F. Yu, T.-Y. Ho and K. Chakrabarty, "Testing of flow-based microfluidic biochips: Fault modeling, test generation, and experimental demonstration", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 33, pp. 1463-1475, October 2014.
188. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "An optimal two-mixer dilution engine with digital microfluidics for low-power applications", Journal of Low Power Electronics, vol. 10, pp. 506-518, September 2014.
189. W. -C. Lien, K.-J. Lee, T.-Y. Hsieh and K. Chakrabarty, "Efficient LFSR reseeding based on internal-response feedback", Journal of Electronic Testing: Theory and Applications, vol. 30, pp. 673-685, December 2014.
190. S. Roy, P. P. Chakrabarti, K. Chakrabarty and B. B. Bhattacharya, "Waste-aware single-target dilution of a biochemical fluid using digital microfluidic biochips, Integration, The VLSI Journal, vol. 51, pp. 194-207, September 2015.

     2015

191. Y. Luo, B. B. Bhattacharya, T.-Y. Ho and K. Chakrabarty, "Design and optimization of a cyberphysical digital-microfluidic biochip for the polymerase chain reaction", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 29-42, January 2015.
192. R. Wang, K. Chakrabarty and S. Bhawmik, "Interconnect testing and test-path scheduling for interposer-based 2.5D ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 122-135, January 2015.
193. M. Agrawal, K. Chakrabarty and R. Widialaksono, "Reuse-based optimization for pre-bond and post-bond testing of 3D-stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 136-149, January 2015.
194. B. Noia, S. Panth, K. Chakrabarty and S. K. Lim, "Scan test of die logic in 3D ICs using TSV probing", IEEE Transactions on VLSI Systems, vol. 33, pp. 317-330, February 2015.
195. Q. Duan, J. Zeng, K. Chakrabarty and G. Dispoto, "Data-driven optimization of order-admission policies in a digital print factory", ACM Transactions on Design Automation of Electronic Systems, vol. 20, Article 21, February 2015.
196. Q. Duan, J. Zeng, K. Chakrabarty and G. Dispoto, "Accurate predictions of process-execution time and process status based on support-vector regression for enterprise information systems", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 354-366, March 2015.
197. F. Vartziotis, X. Kavousianos, K. Chakrabarty, A. Jain and R. Parekhji, "Time-division multiplexing for testing DVS-based SoCs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 668-681, April 2015.
198. Q. Duan, J. Zeng, K. Chakrabarty and G. Dispoto, "Real-time production scheduler for digital-print-service providers based on a dynamic incremental evolutionary algorithm", IEEE Transactions on Automation Science and Engineering, vol. 12, pp. 701-715, April 2015.
199. S. Roy, P. P. Chakrabarti, S. Kumar, K. Chakrabarty and B. B. Bhattacharya, "Layout-aware mixture preparation of biochemical fluids on application-specific using digital microfluidic biochips", ACM Transactions on Design Automation of Electronic Systems, vol. 20, pp. 1-34, June 2015.
200. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Information-theoretic syndrome evaluation, statistical root-cause analysis, and correlation-based feature selection for guiding board-level fault diagnosis", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol 34, pp. 1014-1026, June 2015.
201. M. Agrawal and K. Chakrabarty "Test-cost modeling and optimal test-flow selection of 3D-stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 1523-1536, September 2105.
202. F. Firouzi, F. Ye, K. Chakrabarty and M. Tahoori, "Aging- and variation-aware delay monitoring using representative critical path selection", ACM Transactions on Design Automation of Electronic Systems, vol 20, June 2015.
203. S. Deutsch, K. Chakrabarty and E. J. Marinissen, "Robust optimization of test-access architectures under realistic scenarios", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 34, pp. 1873-1884, November 2015.
204. R. Wang, K. Chakrabarty and S. Bhawmik, "Built-in self-test and test scheduling for interposer-based 2.5D IC", ACM Transactions on Design Automation of Electronic System, vol. 20, pp. 1-24, September 2015.
205. Q. Duan, A. Koneru, J. Zeng, K. Chakrabarty and G. Dispoto, "Accurate analysis and prediction of enterprise service-level performance", ACM Transactions on Design Automation of Electronic Systems, vol. 20, September 2015.
206. M. Ibrahim and K. Chakrabarty, "Efficient error recovery in cyberphysical digital-microfluidic biochips", IEEE Transactions on Multiscale Computing Systems, vol. 1, pp. 46-58, March 2015. (Showcased in IEEE Computer in June 2016 as ``Spotlight on Transactions''.)
207. P. Pop, I. E. Araci and K. Chakrabarty, "Continuous-flow biochips: Technology, physical design methods and testing", IEEE Design & Test, vol. 32, pp. 8-19, Dec 2015.
208. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty and B. B. Bhattacharya, "Off-line washing schemes for residue removal in digital microfluidic biochips", ACM Transactions on Design Automation of Electronic Systems, vol. 21, November 2015.

     2016

209. D. Xiang, K. Chakrabarty and H. Fujiwara, "Multicast-based testing and thermal-aware test scheduling for 3D ICs with a stacked network-on-chip", accepted for publication in IEEE Transactions on Computers, April 2015.
210. M. Agrawal, K. Chakrabarty and B. Eklow, "A distributed, reconfigurable, and reusable BIST infrastructure for test and diagnosis of 3D-stacked ICs", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 309-322, February 2016.
211. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Adaptive board-level functional-fault diagnosis using incremental decision trees", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 323-336, February 2016.
212. Z. Li, T.-Y. Ho and K. Chakrabarty, "Optimization of 3D digital microfluidic biochips for the multiplexed polymerase chain reaction", ACM Transactions on Design Automation of Electronic Systems, vol. 21, Issue 2, Article 25, January 2016.
213. K. Hu, T.-Y. Ho and K. Chakrabarty, "Wash optimization and analysis for cross-contamination removal under physical constraints in flow-based microfluidic biochips", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 559-572, April 2016.
214. S. Jin, F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Efficient board-level functional-fault diagnosis with missing syndromes", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 985-998, June 2016.
215. F. Ye, F. Firouzi, Y. Yang, K. Chakrabarty and M. B. Tahoori, "On-chip droop-induced circuit delay prediction based on support-vector machines", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 665-678, April 2016.
216. K. Hu, B. B. Bhattacharya and K. Chakrabarty, "Fault diagnosis for leakage and blockage defects in flow-based microfluidic biochips", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2015.
217. T. Li, F. Xie, X. Liang, Q. Xu, K. Chakrabarty, N. Jing and L. Jiang, "A Novel Test Method for Metallic CNTs in CNFET-Based SRAM", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 35, pp. 1192-1205, July 2016.
218. S. S. Ali, M. Ibrahim, O. Sinanoglu, K. Chakrabarty and R. Karri, "Security assessment of cyberphysical digital-microfluidic biochips", IEEE/ACM Transactions on Computational Biology and Bioinformatics, vol. 13, pp. 445-458, May/June 2016.
219. S. Poddar, S. Ghoshal, K. Chakrabarty and B. B. Bhattacharya, "Error-correcting sample preparation with cyberphysical digital microfluidic lab-on-chip", accepted for publication in ACM Transactions on Design Automation of Electronic Systems, March 2016.
220. S. S. Ali, M. Ibrahim, J. Rajendran, O. Sinanoglu and K. Chakrabarty, "Supply-chain security of digital microfluidic biochips" accepted for publication in IEEE Computer, April 2016.
221. T. Xu, T. A. Ding, T.-Y. Ho and K. Chakrabarty, "Control-layer routing and control-pin minimization for flow-based microfluidic biochips", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, May 2016.
222. S. Bhattacharjee, S. Chatterjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty and B. B. Bhattacharya, "Adaptation of biochemical protocols to handle technology-change for digital microfluidics", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, June 2016.
223. M. Ibrahim, K. Chakrabarty and K. Scott, "Synthesis of cyberphysical digital-microfluidic biochips for real-time quantitative analysis", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, July 2016.
224. S. Das, J. R. Doppa, P. P. Pande and K. Chakrabarty, "Design-space exploration and optimization of an energy-efficient and reliable 3D small-world network-on-chip", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2016.
225. R. Wang, G. Li, R. Li, J. Qian and K. Chakrabarty, "ExTest scheduling and optimization for 2.5D SoCs with wrapped tiles", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, August 2016.
226. A. Vijayan, A. Koneru, S. Kimaehr, K. Chakrabarty and M. Tahoori, "Fine-grained aging-induced delay prediction based on the monitoring of run-time stress", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, September 2016.

1993-1997

1. K. Chakrabarty and J. P. Hayes, "Aliasing-free error detection (ALFRED)", Proc. IEEE VLSI Test Symposium, pp. 260-267, April 1993.
2. K. Chakrabarty and J. P. Hayes, "Balance testing of logic circuits", Proc. Int. Symp. Fault-Tolerant Computing, pp. 350-359, June 1993.
3. K. Chakrabarty and J. P. Hayes, "DFBT: A design-for-testability technique based on balance testing", Proc. IEEE/ACM Design Automation Conference, pp. 351-357, June 1994.
4. K. Chakrabarty and J. P. Hayes, "Efficient test response compression for multiple-output circuits", Proc. IEEE Int. Test Conference, pp. 501-510, October 1994.
5. K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal space compaction of test responses", Proc. 1995 IEEE Int. Test Conference, pp. 834-843, October 1995.
6. K. Chakrabarty, B. T. Murray, J. Liu and M. Zhu "Test width compression for built-in self testing", Proc. 1997 IEEE International Test Conference, pp. 328-337, November 1997.
7. V. Iyengar, K. Chakrabarty and B. T. Murray, "Test set encoding for testing sequential circuits", Proc. 1997 IEEE Instrumentation & Measurement Technology Conference, pp. 1442-1447, Ottawa, Canada, May 1997.

   1998

8. V. Iyengar, K. Chakrabarty and B. T. Murray, "Deterministic built-in self testing of sequential circuits using precomputed test patterns", Proc. 1998 IEEE VLSI Test Symposium, pp. 418-423, April 1998.
9. K. Chakrabarty, "Design of optimal linear space compactors for built-in self-test", Proc. 1998 IEEE Instrumentation & Measurement Technology Conference, pp. 413-418, St. Paul, MN, May 1998.

   1999

10. K. Chakrabarty, B. T. Murray and V. Iyengar, "Built-in pattern generation for high-performance circuits using twisted ring counters", 1999 IEEE VLSI Test Symposium, pp. 22-27, 1999.
11. P. F. Flores, H. C. Neto, K. Chakrabarty and J. P. M. Silva, "Test pattern generation for width compression in BIST", Proc. 1999 IEEE International Symposium on Circuits and Systems, pp. 114-118, Orlando, FL, May 1999.
12. S. R. Das, T. Barakat, E. M. Petriu, M. H. Assaf and K. Chakrabarty, "Space compaction revisited", Proc. 1999 IEEE Instrumentation & Measurement Technology Conference, pp. 849-854, Venice, Italy, May 1999.
13. K. Chakrabarty, "Test scheduling for core-based systems", Proc. International Conference on Computer-Aided Design (ICCAD) , pp. 391-394, 1999.
14. K. Chakrabarty and S. R. Das, "Test set embedding for mixed-mode BIST", Proc. 1999 IEEE Instrumentation & Measurement Technology Conference, pp. 1778-1783, Venice, Italy, May 1999.

    2000

15. K. Chakrabarty, "Design of system-on-a-chip test access architectures using integer linear programming", Proc. 2000 IEEE VLSI Test Symposium, pp. 127-134, 2000.
16. M. Seuring and K. Chakrabarty, "Space compaction of test responses for IP cores using orthogonal transmission functions", Proc. IEEE VLSI Test Symposium, pp. 213-219, 2000.
17. A. Chandra and K. Chakrabarty, "Test data compression for system-on-a-chip using Golomb codes", Proc. IEEE VLSI Test Symposium, pp. 113-120, Montreal, 2000
    (Received the James Beausang Memorial Best Student Paper Award)
    
18. K. Chakrabarty and S. Swaminathan, "Built-in self testing of high-performance circuits using twisted-ring counters", Proc. 2000 IEEE International Symposium on Circuits and Systems, pp. I-72--I-76, 2000.
19. K. Chakrabarty, "Design of system-on-a-chip test access architectures under place-and-route and power constraints", Proc. IEEE/ACM Design Automation Conference (DAC), pp. 432-437, 2000.
20. S. R. Das, J. Liang, M. Sudarma, E. M. Petriu, W. B. Jone and K. Chakrabarty, "Increasing fault coverage using a new probability measure in output compaction based on switching theory formulation", Proc. IASTED Conference on Modeling, Identification and Control, pp. 589-596, Innsbruck, Austria, February 2000.
21. S. R. Das, J. Liang, E. M. Petriu, W. B. Jone and K. Chakrabarty, "Data compression in space under generalized mergeability based on concepts of cover table and frequency ordering", Proc. Instrumentation and Measurement Technology Conference, pp. 217-222, Baltimore, MD, May 2000.
22. H. Date, V. Iyengar, K. Chakrabarty and M. Sugihara, "Mathematical modeling of intellectual property protection using partially-mergeable cores", Proc. IEEE International Conference on Parallel and Distributed Processing Techniques and Applications, pp. 611-617, 2000.

    2001

23. H. Qi, S. S. Iyengar and K. Chakrabarty, "Distributed multi-resolution data integration using mobile agents", Proc. IEEE Aerospace Conference, vol. 3, pp. 1133-1141, 2001.
24. K. Chakrabarty, R. Mukherjee and A. Exnicios, "Synthesis of transparent circuits for hierarchical and system-on-a-chip test", Proc. IEEE International Conference on VLSI Design, pp. 431-436, Bangalore, India, January 2001.
25. V. Swaminathan and K. Chakrabarty, "Real-time task scheduling for energy-aware embedded systems", IEEE Real-Time Systems Symposium (Work-In-Progress Sessions), Orlando, FL, November 2000.
26. V. Swaminathan and K. Chakrabarty, "Investigating the effect of voltage switching on low-energy task scheduling in hard real-time systems", Proc. Asia South Pacific Design Automation Conference, pp. 251-254, 2001.
27. B. B. Bhattacharya, A. Dmitriev, M. Goessel and K. Chakrabarty, "Synthesis of single-output space compactors with application to scan-based IP cores", Proc. Asia South Pacific Design Automation Conference, pp. 496-501, 2001.
28. T. Zhang, K. Chakrabarty and R. B. Fair, "Design of reconfigurable composite microsystems based on hardware/software co-design principles", Proc. International Conference on Modeling and Simulation of Microsystems, pp. 148-152, 2001.
29. J. Ding, K. Chakrabarty and R. B. Fair, "Reconfigurable microfluidic system architecture based on two-dimensional electrowetting arrays", Proc. International Conference on Modeling and Simulation of Microsystems, pp. 181-185, 2001.
30. A. Chandra and K. Chakrabarty, "Efficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding", Proc. Design Automation and Test in Europe (DATE) Conference, pp. 145-149, 2001.
    (Received Best Paper Award)
31. A. Chandra, K. Chakrabarty and S. R. Das, "On using twisted-ring counters for testing embedded cores in system-on-a-chip designs", Proc. IEEE Instrumentation and Measurement Technology Conference, PP. 216-220, 2001.
32. S. R. Das, M. H. Assaf, E. M. Petriu, W.-B. Jone and K. Chakrabarty, "A novel approach to designing aliasing-free space compactors based on switching theory formulation using a new probability measure under generalized mergeability", Proc. IEEE Instrumentation and Me asurement Technology Conference, pp. 198-203, May 2001.
33. K. Chakrabarty, S. S. Iyengar, H. Qi and E. Cho, "Coding theory framework for target location in distributed sensor networks", Proc. International Symposium on Information Technology: Coding and Computing, pp. 130 -134, 2001.
34. A. Morosov, K. Chakrabarty, B. B. Bhattacharya and M. Goessel, "Design of parameterizable error-propagating space compactors for response observation", Proc. IEEE VLSI Test Symposium, pp. 48-53, 2001.
35. V. Iyengar and K. Chakrabarty, "Precedence-based, preemptive, and power-constrained test scheduling for system-on-a-chip", Proc. IEEE VLSI Test Symposium, pp. 368-374, 2001.
36. A. Chandra and K. Chakrabarty, "Frequency-directed run-length (FDR) codes with application to system-on-a-chip test data compression", Proc. IEEE VLSI Test Symposium, pp. 42-47, 2001.
37. K. Chakrabarty and S. S. Iyengar, "Sensor placement in distributed sensor networks using a coding theory framework", Proc. IEEE International Symposium on Information Theory, p. 157, 2001.
38. S. Swaminathan and K. Chakrabarty, "A deterministic scan-BIST architecture with application to field testing of high-availability systems", Proc. IEEE Custom Integrated Circuits Conference, pp. 259-262, May 2001.
39. V. Swaminathan, K. Chakrabarty and S. S. Iyengar, "Dynamic I/O power management for hard real-time systems", Proc. International Symposium on Hardware/Software Co-Design (CODES), pp. 237-242, April 2001.
40. A. Chandra and K. Chakrabarty, "Combining low-power scan testing and test data compression for system-on-a-chip", Proc. IEEE/ACM Design Automation Conference (DAC), pp. 166-169, June 2001.
41. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test wrapper and test acess mechanism co-optimization for system-on-a-chip", Proc. IEEE International Test Conference, pp. 1023-1032, 2001.
42. H. Qi, X. Wang, S. S. Iyengar and K. Chakrabarty, "Multisensor data fusion in distributed sensor networks using mobile agents", Proc. International Conference on Information Fusion (FUSION 2001), pp. TuC2-11--TuC2-16, 2001.

    2002

43. T. Zhang, K. Chakrabarty and R. B. Fair, System performance evaluation with SystemC for two PCR microelectrofluidic systems", Proc. International Conference on Modeling and Simulation of Microsystems, pp. 48--53, 2002.
44. T. Zhang, K. Chakrabarty and R. B. Fair, "Integrated hierarchical design of microelectrofluidic systems using SystemC", Proc. International Conference on Modeling and Simulation of Microsystems, pp. 144-149, 2002.
45. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Efficient wrapper/TAM Co-optimization for large SOCs", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 491-498, 2002.
46. A. Chandra and K. Chakrabarty, "Test resource partitioning and reduced pin-count testing based on test data compression", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 598-603, 2002.
47. C. Liu, K. Chakrabarty and M. Goessel, "An interval-based diagnosis scheme for identifying failing vectors in a scan-BIST Environment", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 382-386, 2002.
48. A. Chandra, K. Chakrabarty and R. A. Medina, "How effective are compression codes for reducing test data volume?", Proc. IEEE VLSI Test Symposium, pp. 91-96, 2002.
49. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "On using rectangle packing for SOC wrapper/TAM co-optimization", Proc. IEEE VLSI Test Symposium, pp. 253-258, 2002.
50. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Integrated wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs", Proc. IEEE/ACM Design Automation Conference, pp. 685-690, 2002.
51. A. Chandra and K. Chakrabarty, "Reduction of SOC test data volume, scan power and testing time using alternating run-length codes", Proc. IEEE/ACM Design Automation Conference, pp. 673-678, 2002.
52. V. Swaminathan and K. Chakrabarty, "Dynamic I/O power management in real-time systems", Proc. International Conference on Information Fusion (FUSION 2002), pp. 965-972, 2002.
53. V. Swaminathan and K. Chakrabarty, "Pruning-based energy-optimal device scheduling in hard real-time systems", Proc. International Symposium on Hardware/Software Co-Design, pp. 175-180, 2002.
54. S. S. Dhillon, K. Chakrabarty and S. S. Iyengar, "Sensor placement for grid coverage under imprecise detections", Proc. International Conference on Information Fusion (FUSION 2002), pp. 1581-1587, 2002.
55. V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "Test resource optimization for multi-site testing of SOCs under ATE memory depth constraints", Proc. IEEE International Test Conference, pp. 1159-1168, 2002.
56. E. J. Marinissen, V. Iyengar and K. Chakrabarty, "A set of benchmarks for modular testing of SOCs", Proc. IEEE International Test Conference, pp. 519-528, 2002.
57. V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Recent advances in TAM optimization, test scheduling, and test resource management for modular testing of core-based SOCs" (invited paper), Proc. IEEE Asian Test Symposium, pp. 320-325, 2002.
58. A. Dmitriev, M. Goessel and K. Chakrabarty, "Robust space compaction of test responses", Proc. IEEE Asian Test Symposium, pp. 254-259, 2002.
59. V. Swaminathan, C. B. Schweizer, K. Chakrabarty and A. A. Patel, "Experiences in implementing an energy-driven task scheduler in RT-linux", Proc. Real-Time and Embedded Technology and Applications Symposium, pp. 229-239, 2002.
60. Y. Zou and K. Chakrabarty, "Sensor deployment and target localization for tactical surveillance", Proc. Army Science Conference, Paper ID: OP-12, 2002.
61. S. S. Dhillon and K. Chakrabarty, "A fault-tolerant approach to sensor deployment in distributed sensor networks", Proc. Army Science Conference, Paper ID: JP-05, 2002.
62. Y. Zhang and K. Chakrabarty, "Macromodeling of battery discharge and recovery for mobile embedded systems", Proc. Army Science Conference, Paper ID: FP-06, 2002.

    2003

63. Y. Zou and K. Chakrabarty, "Sensor deployment and target localization based on virtual forces", IEEE Infocom Conference, pp. 1293-1303, 2003.
64. C. Liu and K. Chakrabarty, "Compact dictionaries for fault diagnosis in BIST", Proc. IEEE International Symposium on Quality Electronic Design, pp. 105-110, 2003.
65. D. K. Pradhan, C. Liu and K. Chakrabarty, "EBIST: A novel test generator with built-in fault detection capability", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 220-224, 2003.
66. V. Iyengar, A. Chandra, S. Schweizer and K. Chakrabarty, "A unified approach for SOC testing using test data compression and TAM optimization", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1188-1189, 2003.
67. Y. Zhang and K. Chakrabarty, "Energy-aware adaptive checkpointing in embedded real-time systems", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 918-923, 2003.
68. C. Liu and K. Chakrabarty, "A partition-based approach for identifying failing scan cells in scan-BIST with applications to system-on-chip fault diagnosis", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 230-235, 2003.
69. S. S. Dhillon and K. Chakrabarty, "Sensor placement for effective coverage and surveillance in distributed sensor networks", Proc. IEEE Wireless Communications and Networking Conference, pp. 1609-1614, 2003.
70. Y. Zou and K. Chakrabarty, "Energy-aware target localization in wireless sensor networks", Proc. IEEE International Conference on Pervasive Computing and Communications, pp. 60-67, 2003.
71. V. Iyengar, K. Chakrabarty, M. D. Krasniewski and G. N. Kumar, "Design and optimization of multi-level TAM architectures for hierarchical SOCs", Proc. IEEE VLSI Test Symposium, pp. 299-304, 2003.
72. L. Li and K. Chakrabarty, "Test data compression using dictionaries with fixed-length indices", Proc. IEEE VLSI Test Symposium, pp. 219-224, 2003.
73. V. K. Pamula and K. Chakrabarty, "Cooling of integrated circuits using droplet-based microfluidics", Proc. ACM/IEEE Great Lakes Symposium on VLSI, pp. 84-87, 2003.
74. A. Sehgal, V. Iyengar, M. D. Krasniewski and K. Chakrabarty, "Test cost reduction for SOCs using virtual TAMs and Lagrange multipliers", Proc. IEEE/ACM Design Automation Conference, pp. 738-743, 2003.
75. L. Li and K. Chakrabarty, "Deterministic BIST based on a reconfigurable interconnection network", Proc. IEEE International Test Conference, pp. 460-469, 2003.
76. F. Su, S. Ozev and K. Chakrabarty, "Testing of droplet-based microelectrofluidic systems", Proc. IEEE International Test Conference, pp. 1192-1200, 2003.
77. Y. Zou and K. Chakrabarty, "Uncertainty-aware sensor deployment algorithms for surveillance applications", Proc. Globecom 2003-Next Generation Networks and Internet, pp. 2972-2976, 2003.
78. S. Kajihara, Y. Doi, L. Li and K. Chakrabarty, "On combining pinpoint test set relaxation and run-length codes for reducing test data volume", IEEE Int. Conf. Computer Design (ICCD), pp. 387-392, 2003.
79. L. D. Oliver, K. Chakrabarty and R. R. Brooks, "Locomotion-based dynamic power management in embedded real-time systems", Proceedings of SPIE Volume: 5205, Advanced Signal Processing Algorithms, Architectures, and Implementations XIII, pp. 185-196, 2003.
80. A. Sehgal, S. Ozev and K. Chakrabarty, "TAM optimization for mixed-signal SOCs using test wrappers for analog cores", Proc. IEEE International Conference on CAD, pp. 95-99, 2003.
81. V. Swaminathan and K. Chakrabarty, "Generalized network flow techniques for dynamic voltage scaling in hard real-time systems", Proc. IEEE International Conference on CAD, pp. 21-25, 2003.
82. Y. Zhang, K. Chakrabarty and V. Swaminathan, "Energy-aware fault tolerance in fixed-priority real-time embedded systems", Proc. IEEE International Conference on CAD, pp. 209-213, 2003.
83. Y. Zhang and K. Chakrabarty, "Fault recovery based on checkpointing for hard real-time embedded systems", Proc. IEEE Int. Symp. Defect and Fault Tolerance in VLSI Systems, pp. 320-327, 2003.

    2004

84. Y. Zhang and K. Chakrabarty, "Task feasibility analysis and dynamic voltage scaling in fault-tolerant real-time embedded systems", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1170-1175, 2004.
85. A. Sehgal and K. Chakrabarty, "Efficient modular testing of SOCs using dual-speed TAM architectures", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 422-427, 2004.
86. M. Tehranipour, M. Nourani and K. Chakrabarty, "Nine-coded compression technique with application to reduced pin-count testing and flexible on-chip decompression", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1284-1289, 2004.
87. C. Liu, K. Dwarakanath, K. Chakrabarty and R. D. Blanton, "Compact dictionaries for diagnosis of unmodeled faults in scan-BIST", Proc. IEEE Int. Symposium on VLSI, pp. 173-178, 2004.
88. P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Thermal effects on droplet transport in digital microfluidics with applications to chip cooling", Proc. International Conference on Thermal, Mechanics and Thermomechanical Phenomena in Electronic Systems (iTherm), pp. 649-654, 2004.
89. Y. Zhang, R. P. Dick and K. Chakrabarty, "Energy-aware deterministic fault tolerance in distributed real-time embedded systems", Proc. IEEE/ACM Design Automation Conference, pp. 550-555, 2004.
90. F. Su, S. Ozev and K. Chakrabarty, "Test planning and test resource optimization for droplet-based microfluidic systems", Proc. European Test Symposium, pp. 72-77, 2004.
91. F. Su, S. Ozev and K. Chakrabarty, "Concurrent testing of droplet-based microfluidic systems for multiplexed biomedical assays", Proc. International Test Conference, pp. 883-892, 2004.
92. A. Sehgal, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "IEEE P1500-compliant test wrapper design for hierarchical cores", Proc. International Test Conference, pp. 1203-1212, 2004.
93. F. Su and K. Chakrabarty, "Architectural-level synthesis of digital microfluidics-based biochips", Proc. IEEE International Conference on CAD, pp. 223-228, 2004.

    2005

94. K. Chakrabarty, "Design, testing, and applications of digital microfluidics-based biochips" (embedded tutorial), Proc. IEEE International Conference on VLSI Design, pp. 221-226, 2005.
95. L. Li, K. Chakrabarty, S. Kajihara and S. Swaminathan, "Efficient space/time compression to reduce test data volume and testing time for IP cores", Proc. IEEE International Conference on VLSI Design, pp. 53-58, 2005.
96. Y. Doi, S. Kajihara, X. Wen, L. Li and K. Chakrabarty, "Test compression for scan circuits using scan polarity adjustment and pinpoint test relaxation", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 59-64, 2005.
97. A. Sehgal, F. Liu, S. Ozev and K. Chakrabarty, "Test planning for mixed-signal SoCs with wrapped analog cores", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 137-142, 2005.
98. L. Li and K. Chakrabarty, "Hybrid BIST based on repeating sequences and cluster analysis", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 1142-1147, 2005.
99. F. Su and K. Chakrabarty, "Design of fault-tolerant and dynamically-reconfigurable microfluidic biochips", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 1202-1207, 2005.
100. F. Su, K. Chakrabarty and V. K. Pamula, "Yield enhancement of digital microfluidics-based biochips using space redundancy and local reconfiguration", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 1196-1201, 2005.
101. P. Rosinger, B. Al-Hashimi and K. Chakrabarty, "Rapid generation of thermal-safe test schedules", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 840-845, 2005.
102. F. Su and K. Chakrabarty, "Defect tolerance for gracefully-degradable microfluidics-based biochips", Proc. IEEE VLSI Test Symposium, pp. 321-326, 2005.
103. F. Su and K. Chakrabarty, "Reconfiguration techniques for digital microfluidic biochips", Proc. IEEE Design, Test, Integration and Packaging of MEMS/MOEMS Symposiuum, pp. 143-148, 2005.
104. K. Chakrabarty and F. Su, "Design Automation Challenges for Microfluidics-based biochips'' (invited paper for special session), Proc. IEEE Design, Test, Integration and Packaging of MEMS/MOEMS Symposium, pp. 260-265, 2005.
105. Z. Wang and K. Chakrabarty, "Built-in self-test of molecular electronics-based nanofabrics", Proc. IEEE European Test Symposium, 2005.
106. Q. Xu, N. Nicolici and K. Chakrabarty, "Multi-frequency wrapper design and optimization for embedded cores under average power constraints", Proc. IEEE/ACM Design Automation Conference, pp. 123-128, 2005.
107. F. Su and K. Chakrabarty, "Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, pp. 825-830, 2005.
108. Y. Zou and K. Chakrabarty, "Fault-tolerant self-organization in sensor networks", Proc. International Conference on Distributed Computing in Sensor Systems, Published in Lecture Notes in Computer Science LCNS 3560, pp. 191-205, Springer, 2005.
109. Z. Wang and K. Chakrabarty, "Test data compression for IP embedded cores using selective encoding of scan slices", Proc. IEEE International Test Conference, pp. 581-590, 2005.
110. Z. Wang and K. Chakrabarty, "Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics", Proc. IEEE International Test Conference, pp. 477-486, 2005.
111. F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, "Defect-oriented testing and diagnosis of digital microfluidics-based biochips", Proc. IEEE International Test Conference, pp. 487-496, 2005.
112. P. Y. Paik, V. K. Pamula, M. G. Pollack and K. Chakrabarty, "Coplanar digital microfluidics using standard printed circuit board processes", Proc. International Conference on Miniaturized Chemical and Biochemical Analysis Systems (MicroTAS), 2005.
113. K. Chakrabarty and F. Su, "System-level design automation tools for digital microfluidic biochips", Proc. IEEE International Conference on Hardware-Software Codesign and System Synthesis (invited paper in special session), pp. 201-206, 2005.
114. A. Sehgal, S. Ozev and K. Chakrabarty, "A flexible design methodology for analog test wrappers in mixed-signal SOCs", Proc. IEEE International Conference on Computer Design, pp. 137-142, 2005. (Received Best Paper Award)
115. E. Tafaj, P. Rosinger, B. M. Al-Hashimi and K. Chakrabarty, "Improving thermal-safe test scheduling for core-based systems-on-chip using shift frequency scaling", Proc. Defect and Tolerance in VLSI Systems Symposium, pp. 544-551, 2005.
116. A. Sehgal and K. Chakrabarty, "Test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs", Proc. IEEE International Conference on Computer-Aided Design, pp. 88-93, 2005.
117. K. Chakrabarty, "Synthesis and reconfiguration techniques for digital microfluidics-based biochips" (keynote paper), Proc. International Conference & Exhibition on Micro Electro, Opto, Mechanical Systems and Components (MICRO SYSTEM Technologies), pp. 24-39, 2005.
118. P. Y. Paik, V. K. Pamula and K. Chakrabarty "Heat transfer analysis for adaptive hot-spot cooling of integrated circuits using digital microfluidics", Proc. ASME Int. Mechanical Engineering Congress and Symp., 2005.

     2006

119. A. Sehgal, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "Hierarchy-aware and area-efficient test infrastructure design for core-based system chips", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 285-290, 2006.
120. F. Su, W. Hwang and K. Chakrabarty, "Droplet routing in the synthesis of digital microfluidic biochips", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 323-328, 2006.
121. Z. Wang, K. Chakrabarty and M. Goessel, "Test set enrichment using a probabilistic fault model and the theory of output deviations", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 1275-1280, 2006.
122. T. Zhou and K. Chakrabarty, "Authentication of sensor network flooding based on neighborhood cooperation", Proc. IEEE Wireless Communications and Networking Conference, 2006.
123. L. D. Oliver, K. Chakrabarty and H. Z. Massoud, "An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques", Proc. ACM/IEEE GLSVLSI, pp. 105-110, 2006.
124. W. Hwang, F. Su and K. Chakrabarty, "Automated design of pin-constrained digital microfluidic arrays for lab-on-a-chip applications", Proc. IEEE/ACM Design Automation Conference, pp. 925-930, 2006.
125. S. Samii, E. Larsson, K. Chakrabarty and Z. Peng, "Cycle-accurate test power modeling and its application to SOC test scheduling", Proc. IEEE International Test Conference, Paper 32.1, 2006.
126. S. Bahukudumbi and K. Chakrabarty, "Defect-oriented and time-constrained wafer-level test length selection for core-based SOCs", Proc. IEEE International Test Conference, Paper 19.1, 2006.
127. Z. Wang and K. Chakrabarty, "An efficient test pattern selection method for improving defect coverage with reduced test data volume and test application time", Proc. IEEE Asian Test Symposium, pp. 333-338, 2006.
128. N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel, S. Pravossoudovitch and C. Landrault, "Power-aware test data compression for embedded IP cores", Proc. IEEE Asian Test Symposium, pp. 5-10, 2006.
129. D. Xiang, Y. Zhao, K. Chakrabarty, J. Sun and H. Fujiwara, "Compressing test data for deterministic BIST using a reconfigurable scan architecture", Proc. IEEE Asian Test Symposium, pp. 299-304, 2006.
130. T. Xu and K. Chakrabarty, "Droplet-trace-based array partitioning and a pin assignment algorithm for the automated design of digital microfluidic biochips", Proc. IEEE/ACM International Conference on Hardware/Software Codesign and System Synthesis, pp. 112-117, 2006.
131. K. Chakrabarty, "Automated design of microfluidics-based biochips: connecting biochemistry to electronics CAD", Proc. IEEE International Conference on Computer Design (invited paper), pp. 93-100, 2006.

     2007

132. T. Xu, K. Chakrabarty and F. Su, "Defect-aware synthesis of droplet-based microfluidic biochips", Proc. IEEE International Conference on VLSI Design, pp. 647-652, 2007.
     (Received Best Paper Award)
133. S. Bahukudumbi and K. Chakrabarty, "Test-length selection, reduced pin-count testing, and TAM optimization for wafer-level testing of core-based digital SoCs", IEEE International Conference on VLSI Design, pp. 459-464, 2007.
134. A. Kumar, K. Chakrabarty and C. Rama Mohan, "An ECO technique for removing crosstalk violations in clock networks", Proc. IEEE International Conference on VLSI Design, pp. 283-288, 2007.
135. S. Bahukudumbi, S. Ozev, K. Chakrabarty and V. Iyengar, "A wafer-level defect screening technique to reduce test and packaging costs for "big-D/small-A" mixed-signal SoCs", Proc. IEEE/ACM Asia South Pacific Design Automation Conference, pp. 823-828, 2007.
136. Z. Wang, K. Chakrabarty and S. Wang, "SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling", Proc. Design, Automation and Test in Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364591, pp. 201-206, 2007.
137. T. Xu and K. Chakrabarty, "A cross-referencing-based droplet manipulation method for high-throughput and pin-constrained digital microfluidic arrays", Proc. Design, Automation and Test in Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364651, pp. 552-557, 2007.
138. I. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton, J. Hartung, "Heterogeneous systems on chip and systems in package", Proc. Design, Automation and Test in Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364683, pp. 737-742, 2007.
139. T. Xu and K. Chakrabarty, "Parallel scan-like testing and fault diagnosis techniques for digital microfluidic biochips", Proc. IEEE European Test Symposium, pp. 63-68, 2007.
140. Z. Wang, K. Chakrabarty and M. Bienek, "A seed-selection method to increase defect coverage for LFSR-reseeding-based test compression", Proc. IEEE European Test Symposium, pp. 125-130, 2007.
141. Q. Xu, Y. Zhang and K. Chakrabarty, "SOC test architecture optimization for signal integrity faults on core-external interconnects", Proc. IEEE/ACM Design Automation Conference, pp. 676-681, 2007.
142. T. Xu and K. Chakrabarty, "Integrated droplet routing in the synthesis of microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, pp. 948-953, 2007.
143. K. Chakrabarty, "Digital microfluidics: connecting biochemistry to electronic system design" (invited keynote paper), Proc. ASME International Conference on Nanochannels, Microchannels and Minichannels, 2007.
144. T. Zhou, R. Roy Choudhury, P. Ning and K. Chakrabarty, "Privacy-preserving detection of Sybil attacks in vehicular networks", Proc. Annual International Conference on Mobile and Ubiquitous Systems: Computing, Networking and Services (MOBIQUITOUS 2007), 2007, DOI: 10.1109/MOBIQ.2007.445101.
145. T. Xu and K. Chakrabarty, "Functional testing of digital microfluidic biochips", Proc. IEEE International Test Conference, 2007.
146. Q. Xu, Y. Zhang and K. Chakrabarty, "Test-wrapper designs for the detection of signal-integrity faults on core-external interconnects of SoCs", Proc. IEEE International Test Conference, 2007.
147. T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara, "Thermal-safe test access mechanism and wrapper co-optimization for system-on-chip", Proc. IEEE Asian Test Conference, pp. 187-192, 2007.
148. D. Xiang, K. Chakrabarty, D. Hu and H. Fujiwara, "Scan testing for path delay faults with reduced test data volume, test application time, and hardware cost", Proc. IEEE Asian Test Conference, pp. 329-334, 2007.

     2008

149. S. Bahukudumbi, K. Chakrabarty and R. Kacprowicz, "Test scheduling for wafer-level test-during-burn-in of core-based SoCs", Proc. IEEE Design, Automation and Test in Europe (DATE) Conference, pp. 1103-1106, 2008.
150. A. Larsson, E. Larsson, K. Chakrabarty, P. Eles and Z. Peng, "Test-architecture optimization and test scheduling for SOCs with core-level expansion of compressed test patterns", Proc. IEEE Design, Automation and Test in Europe (DATE) Conference, pp. 188-193, 2008.
151. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Test-pattern grading and pattern selection for small-delay defects", IEEE VLSI Test Symposium, pp. 233-239, 2008.
152. S. Bahukudumbi and K. Chakrabarty, "Test-pattern ordering for wafer-level test-during-burn-in", IEEE VLSI Test Symposium, pp. 193-198, 2008.
153. T. Xu and K. Chakrabarty, "Automated design of digital microfluidic lab-on-chip under pin-count constraints", Proc. ACM International Symposium on Physical Design, pp. 90-98, 2008 (Invited Paper).
154. T. Xu and K. Chakrabarty, "Broadcast electrode-addressing for pin-constrained multi-functional digital microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, pp. 173-178, 2008.
155. Y. Zhao and K. Chakrabarty, "On-line testing of lab-on-chip using digital microfluidic compactors", Proc. IEEE International On-line Testing Symposium, pp. 213-218, 2008.
156. Y. Zhao, T. Xu and K. Chakrabarty, "Built-in self-test and fault diagnosis for lab-on-chip using digital microfluidic logic gates", Proc. IEEE International Test Conference, 2008 (Selected as "Top-10 Paper", and listed in the 2009 conference proceedings).
157. M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Interconnect-aware and layout-oriented test-pattern selection for small-delay defects", Proc. IEEE International Test Conference, 2008.
158. V. Mao, C. Dwyer and K. Chakrabarty, "Fabrication defects and fault models for DNA self-assembled nanoelectronics", Proc. IEEE International Test Conference, 2008 (Selected as "Top-10 Paper", and listed in the 2009 conference proceedings).
159. T. Xu, K. Chakrabarty and V. K. Pamula, "Design and optimization of a digital microfluidic biochip for protein crystallization", Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 297-301, 2008.
160. S. Bahukudumbi and K. Chakrabarty, "Power management for wafer-level test during burn-in", IEEE Asian Test Symposium, pp. 231-236, 2008.
161. A. Larsson, X. Zhang, E. Larsson and K. Chakrabarty, "Core-level compression technique selection and SOC test architecture design", IEEE Asian Test Symposium, pp. 277-282, 2008.
162. D. Mitra, S. Ghoshal, H. Rahaman, B. B. Bhattacharya, D. Dutta Majumder and K. Chakrabarty, "Accelerated functional testing of digital microfluidic biochips", IEEE Asian Test Symposium, pp. 295-300, 2008.
163. Y. Zhang, K. Chakrabarty and T. Xu, "Digital microfluidic logic gates", Proc. 3rd International Conference on Nano-Networks, 2008.
164. X. Wu, Y. Chen, K. Chakrabarty and Y. Xie, "Test-access mechanism optimization for core-based three-dimensional SOCs", Proc. IEEE International Conference on Computer Design, pp. 212-218, 2008.
165. K. Chakrabarty, "Towards fault-tolerant digital microfluidic lab-on-chip: defects, fault modeling, testing, and reconfiguration", Proc. IEEE International Conference on Biomedical Circuits and Systems (invited paper), pp. 329-332, 2008.
166. T. Xu, V. K. Pamula and K. Chakrabarty, "Automated, accurate and inexpensive solution-preparation on a digital microfluidic biochip", Proc. IEEE International Conference on Biomedical Circuits and Systems, pp. 301-304, 2008.

     2009

167. T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara, "Thermal-aware TAM design and test scheduling with cycle-accurate power profiles, test partitioning and bandwidth matching", Proc. IEEE Asia South Pacific Design Automation Conference, pp. 793-798, 2009.
168. Y. Zhao and K. Chakrabarty, "Cross-contamination avoidance for droplet routing in digital microfluidic biochips", Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1290-1295, 2009.
169. M. Yilmaz and K. Chakrabarty, "Seed selection in LFSR-reseeding-based test compression for the detection of small-delay defects", Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1488-1493, 2009.
170. X. Kavousianos and K. Chakrabarty, "Generation of compact test sets with high defect coverage", Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1130-1135, 2009.
171. T. Xu and K. Chakrabarty, "Design-for-testability for digital microfluidic biochips", Proc. IEEE VLSI Test Symposium, pp. 309-314, 2009.
172. H. Fang, K. Chakrabarty, A. Jas, S. Patil and C. Trimurti, "RT-level deviation-based grading of functional test sequences", Proc. IEEE VLSI Test Symposium, pp. 264-269, 2009.
173. L. D. Oliver, K. Chakrabarty and H. Z. Massoud, "Dual-threshold pass-transistor logic design", Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 291-296, 2009.
174. T. Xu and K. Chakrabarty, "Towards design-for-testability for digital microfluidics", Proc. Symposium on Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP), pp. 329-333, 2009.
175. Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, ``Physical defect modeling for fault insertion in system reliability test", Proc. International Test Conference, 2009.
176. H. Fang, K. Chakrabarty and R. Parekhji, "Bit-operation-based seed augmentation for LFSR reseeding with high defect coverage", Proc. IEEE Asian Test Symposium, pp. 331-336, 2009.
177. D. Xiang, B. Yin and K. Chakrabarty, "Compact test generation for small-delay defects using testable-path information", Proc. IEEE Asian Test Symposium, pp. 424-429, 2009.
178. B. Noia, K. Chakrabarty and Y. Xie, "Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs", Proc. IEEE International Conference on Computer Design, pp. 70-77, 2009.
179. L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint", Proc. IEEE International Conference on Computer-Aided Design, pp. 191-196, 2009.
180. Y. Zhao, R. Sturmer, K. Chakrabarty and V.K. Pamula, "Optimization of droplet routing for an n-plex bioassay on a digital microfluidic lab-on-chip", Proc. IEEE International Conference on Biomedical Circuits and Systems, pp. 241-244, 2009.

     2010

181. Y. Zhao, R. Sturmer, K. Chakrabarty and V. K. Pamula, "Synchronization of concurrently-implemented fluidic operations in pin-constrained digital microfluidic biochips", IEEE International Conference on VLSI Design, pp. 69-74, 2010.
     (Received Best Paper Award)
     
182. K. Chakrabarty, "Digital microfluidic biochips: A vision for functional diversity and more than Moore", invited embedded tutorial at IEEE International Conference on VLSI Design, pp. 452-457, 2010.
183. K. Peng, M. Yilmaz, M. Tehranipoor and K. Chakrabarty, "High-quality pattern selection for screening small-delay defects considering process variations and crosstalk", IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1426-1431, 2010.
184. R. A. Shafik, B. M. Al-Hashimi and K. Chakrabarty, "Soft error-aware design optimization of low-power and time-constrained embedded systems", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1462-1467, 2010.
185. S. Balatsouka, V. Tanentes, X. Kavousianos and K. Chakrabarty, "Defect aware X-filling for low-power scan testing", IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 873-878, 2010.
186. Y. Zhao and K. Chakrabarty, "Pin-count-aware online testing of digital microfluidic biochips", IEEE VLSI Test Symposium, pp. 111-116, 2010.
187. Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, "Board-level fault diagnosis using Bayesian inference", IEEE VLSI Test Symposium, pp. 244-249, 2010.
188. K. Peng, J. Thibodeau, M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "A novel hybrid method for SDD pattern grading and selection", IEEE VLSI Test Symposium, pp. 45-50, 2010.
189. B. Noia, S. K. Goel, K. Chakrabarty, E. J. Marinissen, and J. Verbree, "Test-architecture optimization for TSV-based 3D stacked ICs", Proc. IEEE European Test Symposium, pp. 24-29, 2010.
190. Y. Zhao and K. Chakrabarty, "Synchronization of washing operations with droplet routing for cross-contamination avoidance in digital microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, pp. 635-640, 2010.
191. K. Chakrabarty, "Digital microfluidic biochips: A vision for functional diversity and more than Moore", Keynote paper at IEEE International Symposium on VLSI, 2010.
192. A. Sanyal, M. Yilmaz, K. Chakrabarty and H. Fujiwara, "RT-level design-for-testability and expansion of functional test sequences for enhanced defect coverage", Proc. IEEE International Test Conference, 2010.
193. B. Noia, K. Chakrabarty and E. J. Marinissen, "Optimization methods for post-bond die-internal/external testing in 3D stacked ICs", Proc. IEEE International Test Conference, 2010.
194. Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, ``Board-level fault diagnosis using an error-flow dictionary'', Proc. IEEE International Test Conference, 2010.
195. K. Chakrabarty and Y. Zhao, "Towards fault-tolerant and reconfigurable microfluidic biochips", Invited paper at Proc. IEEE Asia South Pacific Quality Electronic Design, 2010.
196. Z. Chen, K. Chakrabarty and D. Xiang, "Capture-power reduction with minimum-violations partitioning for delay testing", Proc. IEEE/ACM International Conference on CAD, pp. 149-154, 2010.
197. T.-Y. Ho, J. Zeng and K. Chakrabarty, "Digital microfluidic biochips: A vision for functional diversity and more than Moore", Proc. IEEE/ACM International Conference on CAD (invited tutorial paper), pp. 578-585, 2010.
198. Y. Chen, D. Niu, Y, Xie and K. Chakrabarty, "Cost-effective integration of three-dimensional (3D) ICs emphasizing testing cost analysis", Proc. IEEE/ACM International Conference on CAD, pp. 471-476, 2010.
199. K. Peng, M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "A noise-aware hybrid method for SDD pattern grading and selection", Proc. IEEE Asian Test Symposium, pp. 331-336, 2010.
200. S. K. Goel, K. Chakrabarty, M. Yilmaz, K. Peng and M. Tehranipoor, "Circuit topology-based test pattern generation for small-delay defects", Proc. IEEE Asian Test Symposium, pp. 307-312, 2010.
201. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty and B. B. Bhattacharya, "Testing of digital microfluidic biochips using improved Eulerization techniques and the Chinese postman problem", Proc. IEEE Asian Test Symposium, pp. 111-116, 2010.
202. Y. Zhao and K. Chakrabarty, "Testing of low-cost digital microfluidic biochips with non-regular array layouts", Proc. IEEE Asian Test Symposium, pp. 27-32, 2010.
203. Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, "Optimization and selection of diagnosis-oriented fault-insertion points for system test", Proc. IEEE Asian Test Symposium, pp. 429-432, 2010.
204. H. Fang, Z. Wang, X. Gu and K. Chakrabarty, "Mimicking of functional state space with structural tests for the diagnosis of board-level functional failures", Proc. IEEE Asian Test Symposium, pp. 421-428, 2010.
205. X. Kavousianos, K. Chakrabarty, E. Kalligeros and V. Tenentes, "Defect coverage-driven window-based test compression", Proc. IEEE Asian Test Symposium, pp. 141-146, 2010.

     2011

206. S. Roy, D. Mitra, B. B. Bhattacharya and K. Chakrabarty, ``Pin-constrained designs of digital microfluidic biochips for high-throughput bioassays'', Proc. IEEE International Symposium on Electronic System Design, 2011.
207. H. Fang, Z. Wang, X. Gu and K. Chakrabarty, "Deterministic test for the reproduction and detection of board-level functional failures", Proc. IEEE/ACM Asia South Pacific Design Automation Conference, pp. 491-496, 2011.
208. Z. Zhang, X. Kavousianos, K. Chakrabarty and Y. Tsiatouhas, "A robust and reconfigurable multi-mode power gating architecture", Proc. IEEE International Conference on VLSI Design, pp. 280-285, 2011.
209. S. Roy, B. B. Bhattacharya, P. P. Chakrabarti and K. Chakrabarty, "Layout-aware solution preparation for biochemical analysis on a digital microfluidic biochip", Proc. IEEE International Conference on VLSI Design, pp. 171-176, 2011.
210. S. Roy, B. B. Bhattacharya and K. Chakrabarty, "Waste-aware dilution and mixing of biochemical samples with digital microfluidic biochips", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1059-1064, 2011.
211. Y. Zhao and K. Chakrabarty, "Co-optimization of droplet routing and pin assignment in disposable digital microfluidic biochips", Proc. ACM International Symposium on Physical Design, 2011.
212. F. Bao, K. Peng, M. Yilmaz, K. Chakrabarty, L. Winemberg, M. Tehranipoor, "Critical fault-based pattern generation for screening SDDs", Proc. IEEE European Test Symposium, 2011.
213. H. Fang, Z. Wang, X. Gu and K. Chakrabarty, "Ranking of suspect faulty blocks using dataflow analysis and Dempster-Shafer theory for the diagnosis of board-level functional failures", Proc. IEEE European Test Symposium, 2011.
214. Z. Zhang, X. Kavousianos, Y. Luo, Y. Tsiatouhas and K. Chakrabarty, "Signature analysis for testing, diagnosis, and repair of multi-mode power switches", Proc. IEEE European Test Symposium, 2011.
215. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty and B. B. Bhattacharya, "On residue removal in digital microfluidic biochips", Proc. ACM GLSVLSI, 2011.
216. M. Agrawal, K. Chakrabarty, J. Zeng, I.-J. Lin, G. Dispoto, "Simultaneous task scheduling and resource binding for digital print automation", IIE Industrial Engineering Research Conference (IERC), 2011.
217. B. Noia and K. Chakrabarty, "Pre-bond probing of TSVs in 3D stacked ICs", Proc. IEEE International Test Conference, 2011.
218. Z. Zhang, K. Chakrabarty, Z. Wang, Z. Wang and X. Gu, "Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks", Proc. IEEE International Test Conference, 2011.
219. M. Agrawal, Q. Duan, K. Chakrabarty, J. Zeng, I.-J. Lin, G. Dispoto and Y.-S. Lee, "Digital print workflow optimization under due-dates, opportunity cost and resource constraints", Proc. IEEE International Conference on Industrial Informatics (INDIN), 2011.
220. Z. Zhang, X. Kavousianos, Y. Luo, Y. Tsiatouhas and K. Chakrabarty, "A BIST solution for testing and repair of multi-mode power switches", Proc. IEEE International On-line Test Symposium, 2011.
221. T.-W. Huang, T.-Y. Ho and K. Chakrabarty, "Reliability-oriented broadcast electrode-addressing for pin-constrained digital microfluidic biochips", IEEE International Conference on Computer-Aided Design, 2011.
222. K. Chakrabarty, R. Bellamy, G. Dispoto and J. Zeng, "The role of EDA in digital print automation and infrastructure optimization" (invited paper), to appear in IEEE International Conference on Computer-Aided Design, 2011.
223. T.-Y. Ho, K. Chakrabarty and P. Pop, "Digital microfluidic biochips: Recent research and emerging challenges", Proc. IEEE CODES+ISSS, 2011.
224. C. Kavousianos, K. Chakrabarty, A. Jain and R. Parekhji, "Test scheduling for multicore SoCs with dynamic voltage scaling and multiple voltage islands", ccepted for publication in Proc. IEEE Asian Test Symposium, 2011.
225. F. Bao, K. Peng, K. Chakrabarty and M. Tehranipoor, "On generation of 1-detect TDF pattern set with significantly increased SDD coverage", Proc. IEEE Asian Test Symposium, 2011.
226. B. Noia and K. Chakrabarty, "Identification of defective TSVs in pre-bond testing of 3D ICs", Proc. IEEE Asian Test Symposium, 2011.
227. S. Zhong, S. Khursheed, B.-M. Al-Hashimi, S. Reddy and K. Chakrabarty, "Analysis of resistive bridge defect delay behavior in the presence of process variation", Proc. IEEE Asian Test Symposium, 2011.
228. N. Karimi, Z. Kong, K. Chakrabarty, P. Gupta and S. Patil, "Testing of clock-domain crossing faults in multi-core system-on-chip", Proc. IEEE Asian Test Symposium, 2011.
229. B. Noia and K. Chakrabarty, "Testing and design-for-testability techniques for 3D integrated circuits" (invited paper), Proc. IEEE Asian Test Symposium, 2011.
230. Y.-L. Hsieh, T.-Y. Ho and K. Chakrabarty, "On-chip biochemical sample preparation using digital microfluidics", Proc. IEEE International Symposium on Biomedical Circuits and Systems, 2011.

     2012

231. M. Richter and K. Chakrabarty, "Test pin count reduction for NoC-based test delivery in multicore SOCs", IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 787-792, 2012.
232. Y. Luo, K. Chakrabarty and T.-Y. Ho, "A cyberphysical synthesis approach for error recovery in digital microfluidic biochips", IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1239-1244, 2012.
233. N. Karimi, K. Chakrabarty, P. Gupta and S. Patil, "Test generation for clock-domain crossing faults in integrated circuits", IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 406-411, 2012.
234. U. S. Syed, K. Chakrabarty, A. Chandra and R. Kapur, "3D-scalanble adaptive scan (3D-SAS)", Proc. IEEE International 3D System Integration Conference, 2012.
235. B. Noia and K. Chakrabarty, "Pre-bond testing of die logic and TSVs in high performance 3D-SICs", Proc. IEEE International 3D System Integration Conference, 2012.
236. M. Zamani, M. B. Tahoori and K. Chakrabarty, "Ping-pong test: compact test vector generation for reversible circuits", Proc. IEEE VLSI Test Symposium, pp. 164-169, 2012.
237. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, S.-S. Chien and K. Chakrabarty, "Accumulator-based output selection for test response compaction", Proc. IEEE International Symposium on Circuits and Systems, pp. 2313-2316, 2012.
238. Z. Zhang, X. Gu, Y. Xie, Z. Wang, Z. Wang and K. Chakrabarty, "Diagnostic system based on support-vector machines for board-level functional diagnosis", Proc. IEEE European Test Symposium, 2012.
239. X. Kavousianos, K. Chakrabarty, A. Jain and R. Parekhji, "Time-division multiplexing for testing SoCs with DVS and multiple voltage islands", Proc. IEEE European Test Symposium, 2012.
240. K. Chakrabarty, S. Deutsch, H. Thapliyal and F. Ye, "TSV defects and TSV-induced circuit failures: The third dimension in test and design-for-test" (invited paper), Proc. IEEE Reliability Physics Symposium, pp. 5F.1.1-5F.1.12, 2012.
241. F. Ye and K. Chakrabarty, "TSV open defects in 3D integrated circuits: Characterization, test, and optimal spare allocation", Proc. IEEE/ACM Design Automation Conference, 2012.
242. C.-Y. Hsu, C.-Y. Kuo, J. C.-M. Li and K. Chakrabarty, "3D IC test scheduling using simulated annealing", Proc. International Symposium on VLSI Design, Automation and Test (VLSI- DAT), 2012.
243. Y. Luo and K. Chakrabarty, "Design of pin-constrained general-purpose digital microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, 2012.
244. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty, B. B. Bhattacharya, "Automated path planning for washing in digital microfluidic biochips", Proc. IEEE International Conference on Automation Science & Engineering, pp. 115-120, 2012.
245. D. Mitra, S. Roy, K. Chakrabarty and B. B. Bhattacharya, "On-chip sample preparation with multiple dilutions using digital microfluidics", Proc. IEEE International Symposium on VLSI, pp. 314-319, 2012.
246. Y. Luo, K. Chakrabarty and T.-Y. Ho, "Dictionary-based error recovery in cyberphysical digital-microfluidic biochips", Proc. IEEE/ACM International Conference on CAD, pp. 369-376, 2012.
247. B. Noia, S. Panth, K. Chakrabarty and S. K. Lim, "Scan test of die logic in 3D ICs using TSV probing", Proc. IEEE International Test Conference, 2012.
248. M. Agrawal, M. Richter and K. Chakrabarty, "A dynamic programming solution for optimizing test delivery in multicore SoCs", Proc. IEEE International Test Conference, 2012.
249. Y.-L. Hsieh, T.-Y. Ho and K. Chakrabarty, "Design methodology for sample preparation on digital microfluidic biochips", Proc. IEEE International Conference on Computer Design, pp. 189-194, 2012.
250. S. Eggersgluess, M. Yilmaz and K. Chakrabarty, "Robust timing-aware test generation using pseudo-boolean optimization", Proc. IEEE Asian Test Symposium, pp. 290-295, 2012.
251. F. Ye, K. Chakrabarty, Z. Zhang and X. Gu, "Adaptive board-level functional fault diagnosis using decision trees", in Proc. IEEE Asian Test Symposium, pp. 202-207, 2012.
252. F. Ye, K. Chakrabarty, Z. Zhang and X. Gu, "Board-level functional fault diagnosis using learning based on incremental support-vector machines", in Proc. IEEE Asian Test Symposium, pp. 208-213, 2012.
253. S. Deutsch, K. Chakrabarty, S. Panth and S. K. Lim, "TSV stress-aware ATPG for 3D stacked ICs", Proc. IEEE Asian Test Symposium, pp. 31-36, 2012 (Received Best Paper Award).
254. V. Guarnieri, F. Fummi and K. Chakrabarty, "Reduced-complexity transition-fault test generation for non-scan circuits through high-level mutant injection", Proc. IEEE Asian Test Symposium, pp. 302-307, 2012.
255. D. Mitra, S. Ghoshal, H. Rahaman, K. Chakrabarty and B. B. Bhattacharya, "On-line error detection in digital microfluidic biochips", Proc. IEEE Asian Test Symposium, pp. 332-337, 2012.
256. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "Low-cost dilution engine for sample preparation using digital microfluidic biochips", Proc. IEEE International Symposium on Electronic Design, pp. 203-307, 2012.

     2013

257. S. Deutsch and K. Chakrabarty, "Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1065-1070, 2013.
258. K. Hu, B.-N. Hsu, A. Madison, K. Chakrabarty and R. B. Fair, "Fault detection, real-time error recovery, and experimental demonstration for digital microfluidic biochips", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 559-564, 2013.
259. X. Kavousianos and K. Chakrabarty, "Testing for SoCs with advanced static and dynamic power-management capabilities", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 737-742, 2013.
260. B. Noia and K. Chakrabarty, "Post-DfT-insertion retiming for delay recovery on inter-die paths in 3D ICs", Proc. IEEE VLSI Test Symposium, pp. 264-269, 2013.
261. M. Agrawal and K. Chakrabarty, "Test-cost optimization and test-flow selection for 3D-stacked ICs", Proc. IEEE VLSI Test Symposium, pp. 276--281, 2013.
262. K. Hu, T.-Y. Ho, and K. Chakrabarty, "Testing of flow-based microfluidic biochips", Proc. IEEE VLSI Test Symposium, pp. 124-129, 2013 (Received Best Paper Award).
263. Y. Luo, K. Chakrabarty and T.-Y. Ho, "Design of cyberphysical digital-microfluidic biochips under completion-time uncertainties in fluidic operations", Proc.. IEEE/ACM Design Automation Conference, 2013.
264. L. Jiang, Q. Xu, F. Ye, K. Chakrabarty and B. Eklow, "On effective and efficient in-field TSV repair for stacked 3D ICs", Proc. IEEE/ACM Design Automation Conference, 2013.
265. S. Deutsch and K. Chakrabarty, "Robust optimization of test-architecture designs for core-based SoCs", Proc. IEEE European Test Symposium, 2013.
266. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Information-theoretic syndrome and root-cause analysis for guiding board-level fault diagnosis", Proc. IEEE European Test Symposium, 2013 (Received Best Paper Award).
267. S. Kumar, S. Roy, P. P. Chakrabarti, B. B. Bhattacharya and K. Chakrabarty, "Efficient mixture preparation on digital microfluidic biochips", Proc. IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, pp. 205-210, 2013.
268. S. Roy, P. P. Chakrabarti, S. Kumar, B. B. Bhattacharya and K. Chakrabarty, "Routing-aware resource allocation for mixture preparation in digital microfluidic biochips", Proc. IEEE International Symposium on VLSI, pp. 165-170, 2013.
269. S. Deutsch, K. Chakrabarty and E. J. Marinissen, "Uncertainty-aware robust optimization of test-access architectures for 3D stacked ICs", Proc. IEEE International Test Conference, 2013.
270. M. Agrawal and K. Chakrabarty, "A graph-theoretic approach for minimizing the number of wrapper cells for pre-bond testing of 3D-stacked ICs", Proc. IEEE International Test Conference, 2013.
271. F. Firouzi, F. Ye, K. Chakrabarty and M. B. Tahoori, "Representative critical-path selection for aging-induced delay monitoring", Proc. IEEE International Test Conference, 2013.
272. Y. Luo, B. Bhattacharya, T.-Y. Ho, and K. Chakrabarty, "Optimization of polymerase chain reaction on a cyberphysical digital microfluidic biochip", Proc. IEEE International Conference on Computer-Aided Design, pp. 622-629, 2013.
273. D. Xiang, G. Liu, K. Chakrabarty and H. Fujiwara, "Thermal-aware test scheduling for NOC-based 3D integrated circuits", Proc. IEEE VLSI-SOC, pp. 96-101, 2013.
274. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "On-chip dilution from multiple concentrations of a sample fluid using digital microfluidics", Proc. IEEE International Symposium on VLSI Design and Test (VDAT), pp. 274-283, 2013.
275. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty and B. B. Bhattacharya, "Eco-friendly sample preparation with concentration gradient on a digital microfluidic biochip", Proc. International Conference on Eco-friendly Computing and Communication Systems (ICECCS), 2013.
276. Z. Zhang, B. Noia, K. Chakrabarty and P. Franzon, "Face-to-face bus design with built-in self-test in 3D ICs", Proc. IEEE 3D Systems Integration Conference, 2013.
277. W.-C. Lien, K.-J. Lee, T.-Y. Hsieh and K. Chakrabarty, "A new LFSR reseeding scheme via internal response feedback", Proc. IEEE Asian Test Symposium, pp. 97-102, 2013.
278. F. Ye, S. Jin, K. Chakrabarty, Z. Zhang and X. Gu, "Handling missing syndromes in board-level functional-fault diagnosis", Proc. IEEE Asian Test Symposium, pp. 73-78, 2013.
279. R. Wang, K. Chakrabarty and W. Eklow "Post-bond testing of the silicon interposer and micro-bumps in 2.5 ICs", Proc. IEEE Asian Test Symposium, pp. 147-152, 2013.
280. C.-J. Shih, S.-A. Hsieh, Y.-C. Lu, J. C.-M. Li, T.-L. Wu and K. Chakrabarty,"Test generation of path delay faults induced by defects in power TSV", Proc. IEEE Asian Test Symposium, pp. 43-48, 2013.
281. S. Bhattacharjee, A. Banerjee, T.-Y. Ho, K. Chakrabarty and B. B. Bhattacharya, "On producing linear dilution gradient of a sample with a digital microfluidic biochip", Proc. IEEE International Symposium on Electronic Design, 2013.
282. S. Roy, B. B. Bhattacharya, S. Ghoshal and K. Chakrabarty, "Optimal two-mixer scheduling in dilution engine on a digital microfluidic biochip", Proc. IEEE International Symposium on Electronic Design, 2013.

     2014

283. K. Hu, T.-Y. Ho and K. Chakrabarty, "Wash optimization for cross-contamination removal in flow-based microfluidic biochips", Proc. IEEE/ACM Asia South Pacific Design Automation Conference, 2014.
284. S. Bhattacharjee, A. Banerjee, K. Chakrabarty and B. B. Bhattacharya, "Correctness checking of bio-chemical protocol realizations on a digital microfluidic biochip", Proc. IEEE International Conference on VLSI Design, pp. 504-509, Jan 2014.
285. F. Vartziotis, C. Kavousianos, K. Chakrabarty, R. Parekhji and A. Jain, "Multi-site test optimization for multi-Vdd SoCs using space- and time-division multiplexing", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1-6, March 2014.
286. F. Ye, F. Firouzi, Y. Yang, K. Chakrabarty and M. Tahoori, "On-chip voltage-droop prediction using support-vector machines", Proc. IEEE VLSI Test Symposium, pp. 282-287, 2014.
287. K. Hu, T.-Y. Ho and K. Chakrabarty, "Test generation and design-for-testability for flow-based mVLSI microfluidic biochips", Proc. IEEE VLSI Test Symposium, pp. 97-102, 2014.
288. M. Agrawal and K. Chakrabarty, "Test-time optimization in NOC-based manycore SOCs using multicast routing", Proc. IEEE VLSI Test Symposium, pp. 276-281, 2014.
289. R. Wang, K. Chakrabarty and S. Bhawmik, "At-speed interconnect testing and test-path optimization in 2.5D ICs", Proc. IEEE VLSI Test Symposium, pp. 151-156, 2014.
290. W.-C. Lien, K.-J. Lee, K. Chakrabarty and T.-Y. Hsieh, "Output selection for test response compaction based on multiple counters", Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2014.
291. W.-C. Lien, K.-J. Lee, K. Chakrabarty and T.-Y. Hsieh, "Output-bit selection with X-avoidance using multiple counters for test-response compaction", Proc. IEEE European Test Symposium, 2014.
292. S. Roy, S. Kumar, P. P. Chakrabarti, B. B. Bhattacharya and K. Chakrabarty, "Demand-driven mixture preparation and droplet streaming using digital microfluidic biochips", Proc. IEEE/ACM Design Automation Conference, 2014.
293. X. Kavousianos and K. Chakrabarty, "Recent advances in single- and multi-site test optimization for DVS-based SOCs", Proc. IEEE International Conference on Design & Technology of Integrated Systems (DTIS), 2014.
294. F. Firouzi, F. Ye, K. Chakrabarty and M. Tahoori, "Chip health monitoring using machine learning", invited paper, Proc. International Symposium on VLSI, pp. 280-283, 2014.
295. S. Deutsch and K. Chakrabarty, "Massive signal tracing using on-chip DRAM for in-system silicon debug", Proc. IEEE International Test Conference, 2014.
296. M. Agrawal and K. Chakrabarty, "A distributed, reconfigurable, and reusable BIST infrastructure for 3D-stacked ICs", Proc. IEEE International Test Conference, 2014.
297. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu, "Knowledge discovery and knowledge transfer in board-level functional fault diagnosis", Proc. IEEE International Test Conference, 2014.
298. K. Hu. T. Anh-Dinh, T.-Y. Ho and K. Chakrabarty, Control-layer optimization for flow-based mVLSI microfluidic biochips", Proc. IEEE/ACM International Conference on Compilers, Architectures and Synthesis of Embedded Systems (CASES), 2014.
299. R. Wang, K. Chakrabarty and S. Bhawmik, "Built-in self-test for interposer-based 2.5D ICs", Proc. IEEE International Conference on Computer Design, pp. 181-188, 2014.
300. Z. Li, T. A. Dinh, T.-Y. Ho and K. Chakrabarty, "Reliability-driven pipelined scan-like testing of digital microfluidic biochips", Proc. IEEE Asian Test Symposium, pp. 57-62, 2014.
301. F. Firouzi, F. Ye, S. Kiamehr, K. Chakrabarty and M. B. Tahoori, "Adaptive mitigation of parameter variations using fine-grained path clustering", Proc. IEEE Asian Test Symposium, pp. 51-56, 2014
302. Z. Li, T.-Y. Ho and K. Chakrabarty, "Optimization of heaters in a digital microfluidic biochip for the polymerase chain reaction", Proc. IEEE THERMINIC, 2014.

     2015

303. S. Deutsch and K. Chakrabarty, "Software-based test and diagnosis of SoCs using embedded and wide-I/O DRAM", Proc. IEEE Asia and South Pacific Design Automation Conference, pp. 532-537, 2015.
304. Z. Li, T.-Y. Ho and K. Chakrabarty, "Design and optimization of 3D digital microfluidic biochips for the polymerase chain reaction", Proc. IEEE Asia and South Pacific Design Automation Conference, pp. 184-189, 2015.
305. F. Ye, Z. Zhang, K. Chakrabarty and X. Gu "Self-learning and adaptive board-level functional fault diagnosis", Proc. IEEE Asia and South Pacific Design Automation Conference, pp. 294-301, 2015.
306. C.-H. Liao, H.-P. Wen and K. Chakrabarty, "An online thermal-constrained task scheduler for 3D multi-core processors", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 351-356, 2015.
307. M. Ibrahim and K. Chakrabarty, "Error recovery in digital microfluidics for personalized medicine", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 247-252, 2015.
308. R. Wang, G. Li, R. Li, J. Qian and K. Chakrabarty, "ExTest scheduling for 2.5D system-on-chip integrated circuits", Proc. IEEE VLSI Test Symposium, 2015.
309. K. Hu, B. Bhattacharya and K. Chakrabarty, "Fault diagnosis for flow-based microfluidic biochips", Proc. IEEE VLSI Test Symposium, 2015.
310. F. Xie, X. Liang, X. Qiang, K. Chakrabarty, N. Jing and L. Jiang, "Jump test for metallic CNTs in CNFET-based SRAM", Proc. IEEE/ACM Design Automation Conference, 2015.
311. I. E. Araci, P. Pop and K. Chakrabarty, "Microfluidic very large-scale integration for biochips: Technology, testing and fault-tolerant design", Proc. IEEE European Test Symposium, 2015.
312. F. Firouzi, F. Ye, A. Vijayan, A. Koneru, K. Chakrabarty and M. Tahoori, "Re-using BIST for circuit aging monitoring", Proc. IEEE European Test Symposium (poster, 2-page paper in formal proceedings), 2015.
313. T. Dinh, S. Yamashita, T.-Y. Ho and K. Chakrabarty, "Testing of digital microfluidic biochips with arbitrary layouts", Proc. IEEE European Test Symposium (poster, 2-page paper in formal proceedings), 2015.
314. F. Vartziotis, X. Kavousianos and K. Chakrabarty, "A branch-&-bound algorithm for TAM optimization in multi-Vdd SoCs", Proc. IEEE European Test Symposium (poster, 2-page paper in formal proceedings), 2015.
315. S. Das, J. R. Doppa, D. H. Kim, P. P. Pande and K. Chakrabarty, "Optimizing 3D NoC design for energy efficiency: A machine learning approach", Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 705-712, 2015.
316. O. Keszocze, R. Wille, K. Chakrabarty and R. Drechsler, "A Generic and exact routing methodology for digital microfluidic biochip", Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 874-881, 2015.
317. S. Wang, K. Chakrabarty and M. B. Tahoori, Defect clustering-aware spare-TSV allocation for 3D ICs", Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 307-314, 2015.
     (Received Best Paper Award)
318. A. Koneru, A. Vijayan, K. Chakrabarty and M. B. Tahoori, "Fine-grained aging prediction based on the monitoring of run-time stress using DfT infrastructure", Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 51-58, 2015.
319. A. Chatterjee, M. B. Tahoori, K. Chakrabarty, A. Koneru, A. Vijayan and D. Banerjee, "Self-awareness and self-learning for resiliency and real-time systems", Proc. IEEE International Online Test Symposium, pp. 128-131, 2015.
320. K. Hu and K. Chakrabarty, "Testing of flow-based microfluidic biochips", one-page minisymposium paper in Proc. IEEE Engineering in Medicine and Biology Conference (EMBC), 2015.
321. K. Hu, T.-Y. Ho and K. Chakrabarty, "Flow-based biochips: Design for reliability and cross-contamination avoidance", one-page minisymposium paper in Proc. IEEE Engineering in Medicine and Biology Conference (EMBC), 2015.
322. S. Deutsch and K. Chakrabarty, "Contactless pre-bond TSV fault diagnosis using duty-cycle detectors and ring oscillators", Proc. IEEE International Test Conference, 2015.
323. F. Vartziotis, X. Kavousianos, P. Georgiou and K. Chakrabarty, "Test-access-mechanism optimization for multi-Vdd SoCs", Proc. IEEE International Test Conference, 2015.
324. T. A. Dinh, S. Yamashita, T.-Y. Ho and K. Chakrabarty, "A general testing method for digital microfluidic biochips under physical constraints", Proc. IEEE International Test Conference, 2015.
325. Z. Li, S. K. Goel, F. Lee and K. Chakrabarty, "Efficient observation-point insertion for diagnosability enhancement in digital circuits", Proc. IEEE International Test Conference, 2015.
326. S. Deutsch and K. Chakrabarty, "Test and debug solutions for 3D-stacked integrated circuits", Proc. IEEE International Test Conference, 2015.
327. K. Hu, M. Ibrahim, L. Chen, Z. Li, K. Chakrabarty, and R. Fair, "Experimental demonstration of error recovery in an integrated cyberphysical digital-microfluidic platform", Proc. IEEE Biomedical Circuits & Systems Conference, 2015.
328. S. S. Ali, M. Ibrahim, O. Sinanoglu, K. Chakrabarty and R. Karri, "Security implications of cyber-physical digital microfluidic biochips", Proc. IEEE International Conference on Computer Design, pp. 483-486, 2015.
329. T.-Y. Ho, W. Grover, K. Chakrabarty and S. Hu, "Cyber-physical integration in programmable microfluidic biochips", Proc. IEEE International Conference on Computer Design, pp. 224-227, 2015.

     2016

330. S. Wang, K. Chakrabarty and M. Tahoori, "Thermal-aware TSV repair for electromigration in 3D ICs", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1291-1296, 2016.
331. M. Ibrahim, K. Chakrabarty and K. Scott, "Integrated and real-time quantitative analysis using cyberphysical digital-microfluidic biochips", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 630-635, 2016.
332. S. Das, J. R. Doppa, P. P. Pande and K. Chakrabarty, "Reliability and performance trade-offs for 3D NoC-enabled multicore chips", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1429-1432, 2016.
333. R. Wang, Z. Li, S. Kannan and K. Chakrabarty, "Pre-bond testing of the silicon interposer in 2.5D ICs", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 978-983, 2016.
334. S. S. Nuthakki, R. Karmakar, S. Chattopadhyay and K. Chakrabarty, "Optimization of the IEEE 1687 access network for hybrid access schedules", accepted for publication in IEEE VLSI Test Symposium, 2016.
335. A. Vijayan, A. Koneru, M. Ebrahimi, K. Chakrabarty and M. B. Tahoori, "Online soft-error vulnerability estimation for memory arrays", accepted for publication in IEEE VLSI Test Symposium, 2016.
336. R. Wang, B. Bhaskaran, K. Natarajan, A. Abdollahian, K. Narayanun, K. Chakrabarty and A. Sanghani, "A programmable method for low-power scan shift in SoC integrated circuits", accepted for publication in IEEE VLSI Test Symposium, 2016.
337. A. Koneru and K. Chakrabarty, Analysis of electrostatic coupling in monolithic 3D integrated circuits and its impact on delay testing", accepted for publication in IEEE European Test Symposium, 2016.
338. R. Wang and K. Chakrabarty, "A design-for-test solution for monolithic 3D integrated circuits", accepted for publication in IEEE European Test Symposium, 2016.
339. P. Georgiou, F. Vartziotis, X. Kavousianos and K. Chakrabarty, "Two-dimensional time-division multiplexing for 3D-SoCs", accepted for publication in IEEE European Test Symposium, 2016.
340. Z. Li, K. Y.-T. Lai, P.-H. Yu, T.-Y. Ho, K. Chakrabarty, and C.-Y. Lee, "High-level synthesis for micro-electrode-dot-array digital microfluidic biochips", accepted for publication in ACM/IEEE Design Automation Conference (DAC), 2016.
341. M. Ibrahim, C. Boswell, K. Chakrabarty, K. Scott and M. Pajic, "A real-time digital-microfluidic platform for epigenetics", accepted for publication in Proc. IEEE/ACM International Conference on Compilers, Architectures and Synthesis For Embedded Systems (CASES), 2016.
342. S. Jin, Z. Zhang, K. Chakrabarty and X. Gu, "Anomaly Detection Using Time-Series Analysis in a Core Router System", accepted for publication in International Work-Conference on Time Series Analysis (ITISE), 2016.
343. Z. Li, K. Y.-T. Lai, P.-H. Yu, K. Chakrabarty, M. Pajic, T.-Y. Ho and C.-Y. Lee, "Error recovery in a micro-electrode-dot-array digital microfluidic biochip", accepted for publication in ACM/IEEE International Conference on CAD (ICCAD), 2016.
344. R. Wang, S. Deutsch, M. Agrawal and K. Chakrabarty, "The hype, myths, and realities of testing 3D integrated circuits", to appear in ACM/IEEE International Conference on CAD (ICCAD), 2016.
345. S. Das, J. R. Doppa, P. P. Pande and K. Chakrabarty, "Energy-efficient and reliable 3D network-on-chip (NoC): Architectures and optimization algorithms", to appear in ACM/IEEE International Conference on CAD (ICCAD), 2016.
346. Z. Li, K. Y.-T. Lai, P.-H. Yu, K. Chakrabarty, T.-Y. Ho and C.-Y. Lee, "Built-in self-test for micro-electrode-dot-array digital microfluidic biochips", accepted for publication in IEEE International Test Conference, 2016.
347. S. Jin, Z. Zhang, K. Chakrabarty and X. Gu, "Accurate anomaly detection using correlation-based time-series analysis in a core router system", accepted for publication in IEEE International Test Conference, 2016.
348. T. Li, L. Jiang, X. Liang, Q. Xu and K. Chakrabarty, "Defect tolerance for CNFET-based SRAMs", accepted for publication in IEEE International Test Conference, 2016.
349. J. Tang, R. Karri, M. Ibrahim and K. Chakrabarty, "Securing digital microfluidic biochips by randomizing checkpoints", accepted for publication in IEEE International Test Conference, 2016.
350. G. Kadam, M. Rudack, K. Chakrabarty and J. Alt, "Supply-voltage optimization to account for process variations in high-volume manufacturing testing", accepted for publication in IEEE International Test Conference, 2016.
351. D. Xiang, K. Chakrabarty and H. Fujiwara, "A unified test and fault-tolerant multicast solution for network-on-chip designs", accepted for publication in IEEE International Test Conference, 2016.
352. R. Wang and K. Chakrabarty, "Testing of interposer-based 2.5D integrated circuits", to appear in IEEE International Test Conference, 2016.
353. S. Jin, K. Chakrabarty, Z. Zhang, G. Chen and X. Gu, "Anomaly-detection-based failure prediction in a core router system", accepted for publication in Proc. International Conference on Advances in System Testing and Validation Lifecycle (VALID), 2016.
354. S. Wang, R. Wang, K. Chakrabarty and M. B. Tahoori, ``Multicase test architecture and test scheduling for 2.5D ICs'', to appear in Proc. IEEE Asian Test Symposium, 2016.
355. R. Wang and K. Chakrabarty, ``Testing of interposer-based 2.5D integrated circuits: Challenges and solutions'', to appear in Proc. IEEE Asian Test Symposium, 2016.
356. M. Ibrahim and K. Chakrabarty, "Cyberphysical adaptation in digital-microfluidic biochips", to appear in Proc. IEEE Biomedical Circuits and Systems Conference, 2016.
357. S. S. Ali, M. Ibrahim, O. Sinanoglu, K. Chakrabarty and R. Karri, "Microfluidic encryption of on-chip biochemical assays", to appear in Proc. IEEE Biomedical Circuits and Systems Conference, 2016.
358. A. Koneru, S. Kannan and K. Chakrabarty, ``Impact of wafer-bonding defects on monolithic 3D integrated circuits'', to appear in Proc. International Conference on Electrical Performance of Electronic Pakaging and Systems, 2016. 2016.

     2017

359. O. Keszocze, Z. Li, A. Grimmer, R. Wille, K. Chakrabarty and R. Drechsler, "Exact routing for micro-electrode-dot-array digital microfluidic biochips", to appear in Proc. IEEE/ACM Asia South Pacific Design Automation Conference, 2017.
360. A. Vijayan, S. Kiamehr, F. Oboril, K. Chakrabarty and M. Tahoori, "Workload-aware static aging monitoring of timing-critical flip-flops", to appear in Proc. IEEE/ACM Asia South Pacific Design Automation Conference, 2017.
361. W. Huangfu, L. Xia, M. Cheng, X. Yin, T. Tang, B. Li, K. Chakrabarty, Y. Xie, Y. Wang and H. Yang, "Computation-oriented fault-tolerance schemes for RRAM computing systems", to appear in Proc. IEEE/ACM Asia South Pacific Design Automation Conference, 2017.

1. P. F. Flores, H. C. Neto, K. Chakrabarty and J. P. M. Silva, "A model and algorithm for computing minimum-size test patterns", Proc. Cadence Technical Conference (CTC), May 1998.
2. V. Iyengar, A. Chandra and K. Chakrabarty, "University research in system-on-a-chip testing, EDA Vision (www.edavision.com), vol. 1, issue 3, September 2001.
3. S. S. Iyengar, K. Chakrabarty and H. Qi, Guest editorial, Journal of the Franklin Institute, Special Issue on Distributed Sensor Networks, vol. 338, pp. 651-653, September 2001.
4. K. Chakrabarty, Guest editorial, Journal of Electronic Testing: Theory and Applications (JETTA), Special Issue on System-on-a-Chip Testing, vol. 18, August 2002.
5. K. Chakrabarty and E. J. Marinissen, Panel summary on "How useful are the ITC'02 SoC test benchmarks", IEEE Design & Test of Computers, vol. 19, pp. 19-20, September-October 2002.
6. L. Li, K. Chakrabarty, S. Kajihara and S. Swaminathan, "Efficient space/time compression of test data for multiple scan chain designs", poster for the European Test Symposium, 2004 (published in the Informal Symposium Proceedings).
7. L. D. Oliver, K. Chakrabarty and H. Z. Massoud, "An evaluation of the impact of gate oxide tunneling on dual-Vt-based leakage reduction techniques", SRC TECHCON Conf., 2005.
8. K. Chakrabarty and J. Zeng, Guest editorial, IEEE Transactions on CAD/ICAS, Special Issue on Biochips, vol. 25, February 2006.
9. K. Chakrabarty et al., Microfluidics entry in Wikipedia, the free encyclopaedia, 2006 (http://en.wikipedia.org/wiki/Microfluidics).
10. K. Chakrabarty, Column on microfluidics in ACM SIGDA E-Newsletter, 2006.
11. Y. Zhao, D. Xiang and K. Chakrabarty, "Reducing test data volume of deterministic BIST via test-point insertion", poster for the European Test Symposium, 2007 (published in the Informal Symposium Proceedings).
12. Q. Xu, Y. Zhang and K. Chakrabarty, "Test wrapper design for signal integrity faults on core-external interconnects", poster for the European Test Symposium, 2007 (published in the Informal Symposium Proceedings).
13. Section on biochips testing contributed to the chapter: R. Ramadoss, R. Dean and X. Xiong, "MEMS Testing", In L.-T. Wang, C. Stround and N. A. Touba, ed., System-on-Chip Test Architectures: Nanometer Design for Testability, Elsevier, 2007.
14. K. Chakrabarty and S. Sapatnekar, Guest editorial, ACM Journal on Emerging Technologies in Computing Systems, Special Issue on DAC 2006, November 2007.
15. A. R. Lebeck and K. Chakrabarty, Guest editorial, ACM Journal on Emerging Technologies in Computing Systems, Special Issue on DAC 2007, 2008.
16. I. Bahar and K. Chakrabarty, Guest editorial, Joint Special Issue of ACM Journal on Emerging Technologies in Computing Systems and ACM Transactions on Design Automation of Electronic Systems, Special Issue on ICCAD 2006, April 2008.
17. X. Wu, Y. Chen, K. Chakrabarty and Y. Xie, "Test-access solutions three-dimensional SOCs", poster paper in Proc. IEEE International Test Conference, 2008.
18. A. Larsson, E. Larsson and K. Chakrabarty, "SOC test optimization with compression technique selection", poster paper in Proc. IEEE International Test Conference, 2008.
19. B. Noia and K. Chakrabarty, "Pre-bond probing of TSVs in 3D stacked IC", SRC TECHCON Conf., 2011.

1. K. Chakrabarty, B. T. Murray and J. P. Hayes, "Synthesis of built-in self-test circuits with complete fault coverage", IEEE Int. Test Synthesis Workshop, Santa Barbara, CA, May 1995 (unpublished).
2. K. Chakrabarty and J. P. Hayes, "Analysis of accumulator-based compaction of test responses", IEEE Int. On-line Testing Workshop, Nice, France, July 1995.
3. K. Chakrabarty, M. Karpovsky and L. Levitin, "Fault detection and isolation in multiprocessor systems with point-to-point connections", IEEE Workshop on Fault-Tolerant and Distributed Systems, Honolulu, Hawaii, April 1996.
4. B. T. Murray, K. Chakrabarty and M. C. Hansen, "Maximum transparency space compaction (or how to get more than 100\% fault coverage)", IEEE Int. Test Synthesis Workshop, Santa Barbara, May 1996 (unpublished).
5. V. Iyengar, K. Chakrabarty and B. T. Murray, "Built-in self testing with complete fault coverage", IEEE North Atlantic Test Workshop, West Greenwich, RI, May 1997.
6. P. F. Flores, H. C. Neto, K. Chakrabarty and J. P. M. Silva, "A model and algorithm for computing minimum-size test patterns" 1998 European Test Workshop, Barcelona, Spain, May 1998.
7. K. Chakrabarty, "Test access architectures for system-on-a-chip design", 1999 North Atlantic Test Workshop, West Greenwich, RI, May 1999.
8. V. Iyengar, M. Sugihara, H. Date and K. Chakrabarty, "Intellectual property protection using partially-mergeable cores", IEEE Testing Embedded Core-Based Systems (TECS) Workshop, Montreal, Canada, May 2000.
9. A. Chandra and K. Chakrabarty, "On using Golomb codes and internal scan chains for test data compression/decompression in a system-on-a-chip", IEEE Testing Embedded Core-Based Systems (TECS) Workshop, Montreal, Canada, May 2000.
10. K. Chakrabarty, "Incorporating place-and-route and power constraints in system-on-a-chip test access architectures", IEEE North Atlantic Test Workshop, Gloucester, MA, May 2000.
11. V. Iyengar and K. Chakrabarty, "Co-optimization of test wrapper and test access architecture for embedded cores", IEEE European Test Workshop, Stockholm, Sweden, May 2001.
12. V. Iyengar and K. Chakrabarty, "Iterative TAM optimization for system-on-a-chip", IEEE Testing Embedded Core-Based Systems (TECS) Workshop, Los Angeles, CA, May 2001.
13. A. Chandra and K. Chakrabarty, "On using statistical codes for system-on-a-chip test data compression", IEEE Testing Embedded Core-Based Systems (TECS) Workshop, Los Angeles, CA, May 2001.
14. V. Iyengar and K. Chakrabarty, "TAM width sizing and test scheduling to reduce tester data volume for SOCs", IEEE International Test Synthesis Workshop, Santa Barbara, CA, March 2002.
15. V. Iyengar, S. Goel, E.J. Marinissen and K. Chakrabarty, "On SOC test resource optimization for multisite testing using ATE with memory depth constraints", IEEE North Atlantic Test Workshop, 2002.
16. V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "Test resource optimization for multi-site testing of embedded-core-based SOCs using ATE with memory depth constraints", European Test Workshop, 2002.
17. S. S. Dhillon, K. Chakrabarty and S. S. Iyengar, "Sensor placement for effective grid coverage and surveillance", Workshop on Signal Processing, Communications, Chaos and Systems, Newport, RI, 2002.
18. A. Chandra, S. Schweizer, V. Iyengar and K. Chakrabarty, "A unified approach for SOC test resource partitioning using test data compression and TAM optimization", IEEE Test Resource Partitioning Workshop, Baltimore, October 2002.
19. Y. Zou and K. Chakrabarty, "Target localization based on energy considerations in distributed sensor networks", presented at IEEE International Workshop on Sensor Network Protocols and Applications, Anchorage, AK, 2003 (published in formal proceedings with ISBN number).
20. M. Goessel, K. Chakrabarty, V. Ocheretnij and A. Leininger, "Identification of failing vectors using signature analysis with application to scan-BIST", Proc. International Workshop on Design and Diagnostics of Electronic Circuits and Systems, pp. 81-86, 2003 (published in formal proceedings with ISBN number).
21. A. Sehgal, A. Dubey, E. J. Marinissen, C. Wouters, H. Vranken and K. Chakrabarty, "Yield analysis for repairable embedded memories", presented at IEEE European Test Workshop, 2003 (published in formal proceedings with ISBN number).
22. S. Ozev and K. Chakrabarty, "Global test resource partitioning for mixed-signal SOCs", presented at IEEE North Atlantic Test Workshop, 2003.
23. M. Goessel, A. Leininger, K. Chakrabarty and V. Otscheretnij, "Signature analysis for identifying failing vectors", Tagungsband 15. Workshop Testmethoden und Zuverl???ssigkeit von Schaltungen und Systemen, pp. 51-54, Timmendorfer Strand, 2003.
24. A. Sehgal, S. Ozev and K. Chakrabarty, "Cost-oriented test plan deveopment for analog wrappers in SOCs", presented at the IEEE North Atlantic Test Workshop, 2004.
25. S. Chakravarthula, S. S. Iyengar, K. Chakrabarty and V. Swaminathan "An efficient energy-optimal device-scheduling algorithm for hard real-time systems", Proc. 6th Brazilian Workshop on Real-Time Systems, May 2004.
26. K. Chakrabarty and F. Su, "Automated design of digital microfluidics-based biochips", Workshop on MEMS/MST and Their Perspective in Electronic Systems, March 2005.
27. Z. Wang and K. Chakrabarty, "Test data compresion for IP cores using selective encoding of scan slices", presented at the IEEE International Test Synthesis Workshop, Santa Barbara, CA, April 2005 (no formal publication).
28. Z. Wang and K. Chakrabarty, "Using built-in self-test and adaptive recovery for defect tolerance in molecular electronics-based nanofabrics", presented at the IEEE International Test Synthesis Workshop, Santa Barbara, CA, April 2005 (no formal publication).
29. P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Droplet-based hot spot cooling using topless digital microfluidics on a printed circuit board", Proc. IEEE Int. Workshop on Thermal Investigations of ICs and Systems, Belgirate, Lake Maggiore, Italy, 2005.
30. C. Liu, K. Chakrabarty and V. Iyengar, "Identification of Failing Clock Domains in High-Speed System-on-Chip Circuits", IEEE North Atlantic Test Workshop, Essex Junction., VT, 2006
31. S. Bahukudumbi and K. Chakrabarty, "Test-length selection and TAM optimization for wafer-level, reduced pin-count testing of core-based digital SoCs", 7th Workshop on RTL and High Level Testing (WRTLT'06), Fukuoka, Japan, 2007.
32. Z. Wang, K. Chakrabarty and M. Bienek, "A seed-selection method to increase defect coverage for LFSR-reseeding-based test compression", IEEE Test Synthesis Workshop, San Antonio, TX, 2007 (no formal publication).
33. T. Xu, P. Thwar, V. Srinivasan, V. K. Pamula and K. Chakrabarty, "Digital microfluidic biochip for protein crystallization", IEEE-NIH Life Science Systems and Applications Workshop, Bethesda, MD, 2007.
34. X. Wu, P. Falkenstern, K. Chakrabarty and Y. Xie, "Scan-chain design and optimization for three-dimensional integrated circuits", presented at the IEEE International Test Synthesis Workshop, Santa Barbara, CA, April 2008 (no formal publication).
35. H. Fang and K. Chakrabarty, "RT-level grading of functional test sequences", presented at the IEEE North Atlantic Test Workshop, Boxborough, MA, May 2008.
36. Y. Zhao and K. Chakrabarty, ``Fault diagnosis for lab-on-chip using digital microfluidic logic gates'', presented at the IEEE International Mixed-Signal, Sensors, and Systems Test Workshop, Vancouver, Canada, June 2008.
37. D. Mitra, S. Ghoshal, H. Rahaman, B. B Bhattacharya, D. Dutta Majumdar and K. Chakrabarty, "Accelerated functional testing of digital microfluidic biochips", IEEE International Workshop on Design and Test of Nano Devices, Circuits and Systems, Cambridge, MA, September 2008.
38. K. Peng, M. Yilamaz, K. Chakrabarty and M. Tehranipoor, ``Efficient pattern grading for small delay defects in digital integrated circuits'', IEEE North Atlantic Test Workshop, May 2009.
39. B. Noia and K. Chakrabarty, ``Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs'', IEEE North Atlantic Test Workshop, May 2009.
40. T. Zhou, R. Roy Choudhury and K. Chakrabarty, ``Diverse routing: Exploiting social behavior for routing in delay-tolerant networks'', IEEE Workshop on Leveraging Social Patterns for Security, Privacy and Network Architectures, 2009.
41. H. Fang, K. Chakrabarty and H. Fujiwara, "RTL DFT Techniques to Enhance Defect Coverage for Functional Test Sequences", presented at the IEEE High-Level Design, Validation and Test Workshop, 2009.
42. F. Bao, K. Peng, K. Chakrabarty, and M. Tehranipoor, "Increasing SDD coverage without increasing pattern count", presented at the IEEE North Atlantic Test Workshop, 2011.
43. B. Noia and K. Chakrabarty, "Pre-bond probing of TSVs in 3D stacked ICs", presented at the ATE 2020 Workshop, 2011 (no formal publication).