PUBLICATIONS
DISCLAIMER
WARNING: This directory contains pdf/ps files of
articles that may be covered by copyright. You may browse the
articles at your convenience, in the same spirit as you may read a
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laws.
Books
- T. Zhang, K. Chakrabarty and R. B. Fair, "Microelectrofluidic Systems: Modeling and Simulation", CRC Press, Boca Raton, FL, 2002.
- K. Chakrabarty, V. Iyengar and A. Chandra, "Test Resource Partitioning
for System-on-a-Chip", Kluwer Academic Publishers, Norwell, MA, 2002.
- K. Chakrabarty, ed., "SOC (System-on-a-Chip) Testing for Plug and Play Test Automation", Kluwer Academic Publishers, Norwell, MA, 2002.
- K. Chakrabarty and S. S. Iyengar, "Scalable Infrastructure for Distributed Sensor Networks", Springer, 2005.
- K. Chakrabarty and F. Su, "Digital Microfluidic Biochips: Synthesis, Testing, and Reconfiguration Techniques", CRC Press, Boca Raton, FL, 2006.
- K. Chakrabarty and J. Zeng, ed., "Design Automation Methods and
Tools for Microfluidics-Based Biochips", Springer, Dordrecht, The Netherlands, 2006.
- P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Adaptive Cooling of Integrated Circuits using Digital Microfluidics", Artech House, Norwood, MA, 2007.
- S. Bahukudumbi and K. Chakrabarty, Wafer-Level Testing and Test During Burn-In for Integrated Circuits, to be published by Artech House, Norwell, MA, 2009.
- T. Xu and K. Chakrabarty, Digital Microfluidic Biochips: Design and Optimization, to be published by CRC Press, Boca Raton, FL, 2009.
Book Chapters
- K. Chakrabarty, M. G. Karpovsky and L. B. Levitin, "Fault
isolation and diagnosis in multiprocessor systems with point-to-point
connections", In Fault-Tolerant Parallel and Distributed Systems,
D. R. Avresky and D. R. Kaeli, (eds.), pp. 285-301, Kluwer Academic
Publishers, Norwell, MA, 1998.
- Y. Zhang and K. Chakrabarty, "Adaptive checkpointing with dynamic
voltage scaling in embedded real-time systems", In Embedded Software for SoC
, A. Jerraya, S. Yoo, N. Wehn and D. Verkest (eds.), Chapter 33, pp. 449-463, Kluwer Academic Publishers,
Norwell, MA, 2003.
- V. Swaminathan, Y. Zou and K. Chakrabarty, "Dynamic power management
in wireless sensor networks", In Handbook of Sensor Networks, M. Ilyas
and I. Mahgoub (eds.), pp. 29-1--29.34, CRC Press, 2004.
- V. Swaminathan and K. Chakrabarty, "Operating system power
management", In Distributed Sensor Networks, R. R. Brooks
and S. S. Iyengar (eds.), pp. 667-696, CRC Press, 2004.
- Y. Zou and K. Chakrabarty, "Coverage-driven sensor deployment", In
Distributed Sensor Networks, R. R. Brooks
and S. S. Iyengar (eds.), pp. 453-482, CRC Press, 2004.
- T. Zhang, K. Chakrabarty and R. B. Fair,
"A Hierarchical Design
Platform for Microelectrofluidic Systems
(MEFS)",
In MEMS/NEMS
Handbook: Techniques and Applications, C. T. Leondes (ed.),
Springer, Chapter 7, pp. 197--234, 2006.
- Y. Zou and K. Chakrabarty, "Advances in Target Tracking and Active
Surveillance using Wireless
Sensor Networks", In The Handbook of Algorithmic and Theoretical Aspects of
Ad Hoc,
Sensor, and Peer-to-Peer Networks, J. Wu (ed.), Chapter 29, pp. 475--489,
CRC
Press, 2005.
- H. Sabbineni and K. Chakrabarty, "SCARE: A Scalable
Self-Configuration and Adaptive Reconfiguration Scheme for Dense Sensor
Networks", In S. Phoha, T. F. La Porta and C. Griffin, ed., Sensor Network
Operations, IEEE Press, pp. 14-35, pp. 14-35, 2006.
- K. Chakrabarty, "Modular Testing and Built-In Self-Test of Embedded Cores in System-on-Chip Integrated Circuits", In R. Zurawski, ed., The Embedded Systems Handbook, pp. 27-2--27-27, CRC Press, 2006.
- K. Chakrabarty, "Efficient Modular Testing and Test Resource Partitioning for Core-Based SOCs", In B. M. Al-Hashimi, ed., SOC: Next Generation Electronics, pp. 751-790, IEE Press, 2006.
- F. Su, K. Chakrabarty and R. B. Fair, "Microfluidics-based biochips:
Technology issues,
implementation platforms, and design automation challenges", In K. Chakrabarty
and J. Zeng, ed.,
Design Automation Methods and Tools for Microfluidics-Based Biochips,
Springer, 2006.
- C. Liu, K. Chakrabarty and W.-B. Jone, "System/Network-on-Chip Test Architectures",
In L.-T. Wang, C. Stround and N. A. Touba, ed.,
System-on-Chip Test Architectures: Nanometer Design for Testability, Elsevier, 2007.
- F. Su, S. Ozev and K. Chakrabarty, "Test Planning and Test Resource
Optimization
for Droplet-Based Microfluidic Systems",
In M. Tehranipoor, ed.,
Emerging Nanotechnologies:
Test, Defect Tolerance, and Reliability, Springer, 2007.
- F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, "Testing and
Diagnosis of Realistic Defects
in Digital Microfluidic Biochips",
In M. Tehranipoor, ed.,
Emerging Nanotechnologies:
Test, Defect Tolerance, and Reliability, Springer, 2007.
- Z. Wang and K. Chakrabarty, "Built-In Self-Test and Defect Tolerance in Molecular Electronics-Based Nanofabrics",
In M. Tehranipoor, ed.,
Emerging Nanotechnologies:
Test, Defect Tolerance, and Reliability, Springer, 2007.
- S. K. Goel and K. Chakrabary, "Power-Aware BIST and Test Data Compression", In P. Girard, N. Nicolici and X. Wen, ed.,
Power-Aware Testing and Test Strategies for Low Power Devices,
pp. 147-174, Springer, 2010.
Journal Papers
1993-1997
- K. Chakrabarty and J. P. Hayes, "Cumulative balance testing of logic
circuits", IEEE Transactions on VLSI
Systems, pp. 72-83, vol. 3, March 1995.
- K. Chakrabarty and J. P. Hayes, "Balance testing and balance-testable
design of logic circuits", Journal of Electronic Testing: Theory and
Applications, vol. 8, pp. 71-86, May 1996.
- K. Chakrabarty and J. P. Hayes, "Test response compaction
using multiplexed parity trees", IEEE Transactions on Computer-Aided Design
of Integrated Circuits and Systems, vol. 15, pp. 1399-1408, November 1996.
- K. Chakrabarty and J. P. Hayes, "On the quality of accumulator-based
compaction of test responses",
IEEE Transactions on Computer-Aided Design of Integrated Circuits and
Systems,
vol. 16, pp. 916-922, August 1997.
- V. Iyengar and K. Chakrabarty,
``An efficient finite-state machine implementation of Huffman decoders'',
Information Processing
Letters, vol. 64, pp. 271-275, December 1997.
1998
- M. G. Karpovsky, K. Chakrabarty and L. B. Levitin,
"On a new class of
codes
for covering vertices in graphs",
IEEE Transactions on
Information Theory, vol. 44, pp. 599-611, March 1998.
- K. Chakrabarty and J. P. Hayes, ``Balanced boolean functions'',
IEE Proceedings: Computers and Digital Techniques, vol. 145, pp. 52-62,
January 1998.
- K. Chakrabarty, "Zero-aliasing space compaction using linear
compactors with bounded overhead",
IEEE Transactions on
CAD/ICAS, vol. 17, pp. 452-457, May 1998.
- V. Iyengar, K. Chakrabarty and B. T. Murray,
``Huffman encoding of test sets for sequential circuits'',
IEEE Transactions on Instrumentation and Measurement, vol. 47, pp. 21-25, February 1998.
- K. Chakrabarty and J. P. Hayes, "Zero-aliasing space compaction
using multiple parity signatures", IEEE Transactions on
VLSI Systems, vol. 6, pp. 309-313, June 1998.
- K. Chakrabarty and B. T. Murray, "Design of built-in test generator
circuits using width compression", IEEE
Transactions on CAD/ICAS, vol. 17, pp. 1044-1051, October 1998.
- K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal
zero-aliasing
space compaction of test responses", IEEE
Transactions on
Computers, vol. 47, pp. 1171-1187, November 1998.
1999
- M. G. Karpovsky, K. Chakrabarty, L. B. Levitin and D. R. Avresky,
"On the covering of vertices for fault diagnosis in hypercubes",
Information Processing
Letters, vol. 69, pp. 99-103, January 1999.
- V. Iyengar, K. Chakrabarty and B. T. Murray,
"Deterministic built-in pattern generation for sequential circuits",
Journal of Electronic Testing: Theory and Applications, vol. 15, pp. 97-114, August/October, 1999.
2000
- K. Chakrabarty and S. R. Das,
"Test set embedding based on width compression for mixed-mode BIST",
IEEE Transactions on Instrumentation and Measurement, vol. 49, pp. 671-678, June 2000.
- S. R. Das, T. F. Barakat, E. M. Petriu, M. H. Assaf and K. Chakrabarty, "Space compression revisited", IEEE Transactions on Instrumentation and Measurement, vol. 49, pp. 690-705, June 2000.
- K. Chakrabarty,
"Test scheduling for core-based systems using mixed-integer linear
programming",
IEEE Transactions on CAD/ICAS, vol. 19, pp. 1163-1174, October 2000.
- K. Chakrabarty, B. T. Murray and V. Iyengar,
"Deterministic built-in pattern generation for high-performance circuits
using twisted ring counters", IEEE Transactions on VLSI Systems,
vol. 8, pp. 633-636, October 2000.
2001
- K. Chakrabarty, "Optimal
test access architectures for system-on-a-chip",
ACM Transactions on Design Automation of
Electronic Systems, vol. 6, pp. 26-49, January 2001.
- A. Chandra and K. Chakrabarty, "System-on-a-chip test data compression and decompression architectures
based on Golomb codes", IEEE Transactions on CAD/ICAS, vol. 20, pp. 355-368,
March 2001.
- T. Zhang, F. Cao, A. Dewey, R. B. Fair and K. Chakrabarty, "Performance analysis of microelectrofluidic systems using hierarchical
modeling and simulation", IEEE Transactions on Circuits and Systems (Part II: Analog and Digital Signal Processing), vol. 48, pp. 482-491, May 2001.
- V. Iyengar, H. Date, M. Sugihara and K. Chakrabarty,
"Hierarchical intellectual property protection using partially-mergeable
cores",
IEICE Transactions on Fundamentals of
Electronics, Communications
and
Computer Sciences: Special Section on VLSI Design and CAD Algorithms, pp. 2632-2638, November 2001.
- H. Qi, S. S. Iyengar and K. Chakrabarty,
"Distributed sensor fusion--a review of
recent research", Journal of the Franklin Institute, vol. 338, pp. 655-668, September
2001.
- V. Swaminathan and K. Chakrabarty,
"Real-time task scheduling for energy-aware
embedded systems", Journal of the Franklin Institute, vol. 338, pp. 729-750, September
2001.
- H. Qi, S. S. Iyengar and K. Chakrabarty,
"Multi-resolution data integration using mobile agents in distributed sensor
networks", IEEE Transactions on Systems, Man and
Cybernetics (Part C), vol.
31, pp. 383-391, August 2001.
- A. Chandra, K. Chakrabarty and M. C. Hansen, "Efficient
test
application for core-based systems using twisted-ring counters",
VLSI Design, vol. 12, pp. 475-486, December 2001.
- A. Chandra and K. Chakrabarty, "Test resource
partitioning for system-on-a-chip based on test data compression and on-chip
decompression", IEEE
Design and Test of Computers, vol. 18, pp. 80-91, September/October, 2001.
- S. Swaminathan and K. Chakrabarty, "On using
twisted-ring counters for test set embedding in BIST", Journal of Electronic Testing: Theory and
Applications, vol. 17, pp. 530-542, December 2001.
- J. Ding, K. Chakrabarty and R. B. Fair,
"Scheduling of microfluidic operations for reconfigurable two-dimensional
electrowetting arrays", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 20, pp. 1463-1468, December 2001.
2002
- H. Qi, X. Wang, S. S. Iyengar and K. Chakrabarty,
"High performance sensor data integration in distributed sensor networks
using mobile agents",
International Journal of High Performance Computing
Applications, volume 16, no. 3, pp. 325-335, 2002.
- V. Iyengar and K. Chakrabarty,
""Test bus sizing for system-on-a-chip", IEEE Transactions on Computers, vol. 51, pp. 449-459, May 2002.
- T. Zhang, K. Chakrabarty and R. B. Fair,
"Integrated hierarchical design of microelectrofluidic systems using SystemC", Microelectronics Journal, vol. 33, pp. 459-470, May 2002.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen,
"Test wrapper and test access mechanism co-optimization for system-on-a-chip",
Journal of Electronic Testing: Theory and
Applications (JETTA), vol. 18, pp. 213-230, April 2002.
- A. Chandra and K. Chakrabarty, "Low-power scan
testing and test data compression for
system-on-a-chip", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems,
vol. 21, pp. 597-604, May 2002.
- K. Chakrabarty, S. S. Iyengar, H. Qi and E. Cho,
"Grid coverage for surveillance and target location in distributed sensor
networks",
IEEE Transactions on Computers, vol. 51, pp. 1448-1453, December 2002.
- A. Chandra and K. Chakrabarty,
"System-on-a-chip test data compression and decompression based on internal
scan chains and Golomb coding", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems,
vol. 21, pp. 715-722, June 2002.
- T. Zhang, K. Chakrabarty and R. B. Fair, "Design of reconfigurable composite microsystems using hardware/software co-design principles", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 987-995, August 2002.
- B. B. Bhattacharya, A. Dmitriev, M. Goessel and K. Chakrabarty,
"Synthesis of single-output space compactor for scan-based sequential circuits", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 21, pp. 1171-1179, October 2002.
- V. Iyengar and K. Chakrabarty, "System-on-a-chip test scheduling with precedence relationships,
preemption, and power constraints",
IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems,
vol. 21, pp. 1088-1094, September 2002.
- S. R. Das, J. Y. Liang, E. M. Petriu, M. H. Assaf, W.-B. Jone and K.
Chakrabarty, "Data compression in space under generalized mergeability based
on concepts of cover table and frequency ordering", IEEE Transactions on
Instrumentation and Measurement, vol. 51, pp. 150-172, February 2002.
2003
- A. Chandra and K. Chakrabarty, ""Test data compression and test resource partitioning for
system-on-a-chip using frequency-directed run-length (FDR) codes",
IEEE Transactions on Computers, vol. 52, pp. 1076-1088, August 2003.
- K. Chakrabarty, "A synthesis-for-transparency approach for hierarchical
and system-on-a-chip test",
IEEE Transactions on VLSI Systems, vol. 11, pp. 167-179, April 2003.
- A. Chandra and K. Chakrabarty, "A unified approach to reduce SOC test data volume, scan power and testing time", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 352-362, March 2003.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Efficient test access mechanism optimization for system-on-chip", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 635-643, May 2003.
- C. Liu and K. Chakrabarty, ""Failing vector identification based
on overlapping intervals of test vectors in a scan-BIST environment", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 593-604, May 2003.
- V. Swaminathan and K. Chakrabarty, "Energy-conscious, deterministic I/O device scheduling in hard
real-time systems", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 22, pp. 847-858, July 2003.
- Y. Zou and K. Chakrabarty, "Target localization based on energy
considerations in distributed sensor networks",
Ad Hoc Networks, vol. 1, pp. 261-272, 2003.
- K. Chakrabarty and M. Seuring, "Space compaction of test responses using orthogonal transmission functions",
IEEE Transactions on Instrumentation and Measurement, vol. 52, pp. 1353-1362, October 2003.
- S. R. Das, M. Sudama, M. H. Assaf, E. M. Petriu, W.-B. Jone, K. Chakrabarty and M. Sahinoglu, "Parity bit signature in response data compaction and built-in self-testing of VLSI circuits with nonexhaustive test sets",
IEEE Transactions on Instrumentation and Measurement, vol. 52, pp. 1363-1380,
October 2003.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Test access mechanism optimization, test scheduling and
tester data volume reduction for system-on-chip", IEEE Transactions on Computers, vol. 52, pp. 1619-1632, December 2003.
- L. Li, K. Chakrabarty and N. A. Touba, "Test data compression
using dictionaries with selective entries and fixed-length indices", ACM Transactions on Design Automation of Electronic Systems, vol. 8, pp. 470-490, October 2003.
2004
- Y. Zou and K. Chakrabarty, "Sensor deployment and target localization in
distributed sensor networks", ACM Transactions
on Embedded Computing Systems, vol. 3, pp. 61-91, February 2004.
- Y. Zhang and K. Chakrabarty, "Dynamic adaptation for fault tolerance
and power management in embedded
real-time systems", ACM Transactions on
Embedded Computing Systems, vol. 3, pp. 336-360, May 2004.
- T. Zhang, K. Chakrabarty and R. B. Fair, "Behavioral modeling and
performance evaluation of
microelectrofluidics-based PCR systems using SystemC", IEEE
Transactions on Computer-Aided Design of Integrated Circuits & Systems,
vol. 23, pp. 843-858, June 2004.
- Y. Zou and K. Chakrabarty, "Uncertainty-aware and coverage-oriented
deployment for sensor networks",
Journal of Parallel and Distributed Computing, vol. 64, pp. 788-798, July 2004.
- A. Chandra and K. Chakrabarty, "Analysis of test application time
for test data compression methods based on compression codes",
Journal of Electronic Testing: Theory and Applications, vol. 20, pp. 199-212, April 2004.
- Q. Wu, N. S. V. Rao, J. Barhen, S. S. Iyengar, V. K. Vaishnavi, H. Qi and K. Chakrabarty, "On computing mobile agent routes for data fusion in distributed sensor networks", IEEE Transactions on Knowledge and Data
Engineering, vol. 16, pp. 740-753, June 2004.
- C. Liu and K. Chakrabarty, "Compact dictionaries for fault
diagnosis in scan-BIST", IEEE Transactions on
Computers, vol. 53, pp. 775-780, June 2004.
- L. Li and K. Chakrabarty, "Test set embedding for deterministic
BIST using a reconfigurable interconnection network",
IEEE Transactions on Computer-Aided Design of Integrated Circuits &
Systems, vol. 23, pp. 1289-1305, September 2004.
- V. Swaminathan and K. Chakrabarty, "Network flow techniques for
dynamic voltage scaling in hard real-time systems",
IEEE Transactions on Computer-Aided Design of Integrated Circuits & Systems, vol. 23, pp. 1385-1398, October 2004.
- M. Goessel, K. Chakrabarty, V. Ocheretnij and A. Leininger,
"Identification of failing vectors using signature
analysis with application to scan-BIST",
Journal of Electronic Testing: Theory and
Applications, vol. 20, pp. 611-622, December 2004.
- C. Liu and K. Chakrabarty, "Identification of error-capturing scan
cells in scan-BIST with
applications to system-on-chip",
IEEE Transactions on Computer-Aided Design of
Integrated Circuits & Systems, vol. 23, pp. 1447-14459, October 2004.
- A. Sehgal, V. Iyengar and K. Chakrabarty, "SOC test planning using
virtual test access architectures", IEEE Transactions
on VLSI
Systems, vol. 12, pp. 1263-1276, December 2004.
- L. Li and K. Chakrabarty,
"On using exponential-Golomb
codes and subexponential codes for system-on-a-chip test data compression",
Journal of Electronic Testing: Theory and
Applications, vol. 20, pp. 677-670, December 2004.
- H. Sabbineni and K. Chakrabarty, "A survey of
energy-efficient self-organization and data dissemination protocols for
ad hoc sensor networks", Sensor Letters, vol. 2, pp. 194-204, September/December 2004.
2005
- V. Swaminathan and K. Chakrabarty, "Pruning-based,
energy-optimal, deterministic I/O device
scheduling for hard real-time systems", ACM
Transactions on Embedded Computing Systems, vol. 4, pp. 141-167, February 2005.
- K. Chakrabarty, V. Iyengar and M. Krasniewski, "Test planning for
modular testing of hierarchical SOCs", IEEE
Transactions on Computer-Aided Design of
Integrated Circuits & Systems, vol. 24, pp. 435-448, March 2005.
- F. Su, S. Ozev and K. Chakrabarty, "Ensuring the operational
health of
droplet-based microelectrofluidic biosensor systems",
IEEE Sensors, vol. 5, pp. 763-773, August 2005.
- H. Sabbineni and K. Chakrabarty, "Location-aided flooding: An energy-efficient data dissemination protocol for wireless sensor networks",
IEEE Transactions on Computers, vol. 54, pp. 36-46, January 2005.
- K. Chakrabarty, "Low-cost modular testing and test resource
partitioning for SOCs" (invited paper), IEE Proceedings: Computers and
Digital Techniques, vol. 152 pp. 427-441, May 2005.
- H. M. F. AboElFotoh, S. S. Iyengar and K. Chakrabarty, "Computing reliability
and message delay for
cooperative wireless distributed sensor networks subject to
random failures", IEEE Transactions on
Reliability, vol. 54, pp. 145-155, 2005.
- A. Sehgal, A. Dubey, E. J. Marinissen, C. Wouters, H. Vranken and K.
Chakrabarty, "Redundancy modeling and array yield
analysis for repairable embedded memories",
IEE Proceedings: Computers and Digital
Techniques, vol. 152, pp. 97-106, January 2005.
- M. Tehranipoor, M. Nourani and K. Chakrabarty, "Nine-coded
compression technique for testing embedded cores in SoCs", IEEE Transactions on VLSI Systems, vol. 13, pp. 719-731, June 2005.
- Y. Zou and K. Chakrabarty, "A distributed coverage- and
connectivity-centric technique for selecting active nodes in
wireless sensor networks", IEEE Transactions on Computers, vol. 54, pp. 978-991,
August 2005.
- C. Liu and K. Chakrabarty, "Design and analysis of compact
dictionaries for diagnosis in scan-BIST",
IEEE Transactions on VLSI Systems, vol. 13, pp. 979-984, August 2005.
- L. Li, K. Chakrabarty, S. Kajihara and S. Swaminathan, "A
three-stage compression approach
to reduce test data volume and testing time for IP cores in SOCs", IEE Proceedings: Computers and Digital
Techniques, vol. 152, pp. 704-712, November 2005.
- K. Chakrabarty and J. Zeng, "Design automation for microfluidics-based
biochips", ACM Journal on Emerging Technologies
in Computing Systems, vol. 1, pp. 186-223, December 2005.
2006
- Y. Zhang and K. Chakrabarty,
"A unified approach for fault tolerance and dynamic power management in
real-time embedded systems", IEEE Transactions
on
Computer-Aided Design of Integrated Circuits & Systems, vol. 25, pp. 111-125, January
2006.
- F. Su, K. Chakrabarty and R. B. Fair, "Microfluidics-based biochips:
technology issues, implementation platforms, and design automation challenges",
IEEE Transactions on Computer-Aided Design of Integrated Circuits
& Systems, vol. 25, pp. 211-223, February
2006.
- F. Su, S. Ozev and K. Chakrabarty, "Concurrent testing of
digital microfluidics-based biochips", ACM
Transactions on Design Automation of Electronic Systems, vol 11, pp. 442-464, April 2006.
- P. Rosinger, B. M. Al-Hashimi and K. Chakrabarty, "Thermal-safe
test scheduling for core-based system-on-chip
integrated circuits", IEEE Transactions on
Computer-Aided Design of
Integrated Circuits & Systems, vol. 25, pp. 2502-2512,
November 2006.
- A. Sehgal, S. Ozev and K. Chakrabarty, "
Test infrastructure design
for
mixed-signal SOCs with wrapped analog cores",
IEEE Transactions on VLSI Systems, vol. 14, pp. 292-304, March 2006.
- F. Su, S. Ozev and K. Chakrabarty,
"Test planning and test resource optimization for droplet-based microfluidic
systems",
Journal of Electronic Testing: Theory and
Applications, vol. 22, pp. 199-210, April 2006.
- F. Su and K. Chakrabarty, "Defect tolerance based on graceful
degradation and dynamic
reconfiguration for digital microfluidics-based biochips",
IEEE Transactions on
Computer-Aided Design of
Integrated Circuits & Systems, vol. 25, pp. 2944-2953, December 2006.
(Received IEEE Circuits and Systems Society Outstanding Young
Author Award, 2008)
- F. Su and K. Chakrabarty, "Module placement for fault-tolerant
microfluidics-based biochips",
ACM Transactions on Design Automation of
Electronic Systems, vol. 11, pp. 682-710, 2006.
- F. Su and K. Chakrabarty, "Yield enhancement of reconfigurable
microfluidics-based biochips using
interstitial redundancy", ACM Journal on
Emerging Technologies in Computing Systems, vol. 2, pp. 104-128, April 2006.
- A. Wuertemberber, P. Rosinger, B. Al-Hashimi and K. Chakrabarty, "Cost model-driven test resource partitioning for SoCs", IEE Electronics Letters, pp. 915-916, August 3, 2006.
2007
- A. Sehgal and K. Chakrabarty, "Optimization of dual-speed TAM
architectures for efficient modular testing of SOCs", IEEE Transactions on Computers, vol. 56, pp. 120-133, January 2007.
- L. Li, Z. Wang and K. Chakrabarty, "Scan-BIST based on
cluster analysis and the encoding of repeating sequences", ACM Transactions on Design Automation of
Electronic Systems, vol. 12, DOI Bookmark: 10.1145/1188275.1188279, January 2007 (Article 4).
- Z. Wang and K. Chakrabarty,
"Built-in self-test and defect tolerance in molecular electronics-based
nanofabrics",
Journal of Electronic Testing: Theory and
Applications, vol. 23, pp. 145-161, June 2007.
- F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty,
"Testing and diagnosis of realistic defects in digital microfluidic biochips",
Journal of Electronic Testing: Theory
and
Applications, vol. 23, pp. 219-233, June 2007.
- Y. Zou and K. Chakrabarty, "Redundancy analysis and a distributed
self-organization protocol for
fault-tolerant wireless sensor networks",
International Journal of Distributed Sensor Networks,
vol. 3, pp. 243-272, July 2007.
- Y. Zou and K. Chakrabarty, "Distributed mobility management for
target
tracking in mobile sensor networks", IEEE
Transactions on Mobile Computing, vol. 8, pp. 872-887, August 2007.
- Q. Xu, N. Nicolici and K. Chakrabarty, "Test wrapper design and
optimization under power constraints for embedded cores with multiple clock
frequencies", IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 26, pp. 1539-1547, August 2007.
- T. Xu, W. Hwang, F. Su and K. Chakrabarty,
"Automated design of pin-constrained digital microfluidic biochips under droplet-interference constraints",
ACM Journal on
Emerging Technologies in Computing Systems, vol. 3, Article 14, November 2007
(DOI 10.1145/1295231.1295235).
- S. Bahukudumbi and K. Chakrabarty, "Wafer-level modular testing of
core-based SOCs",
IEEE Transactions on
VLSI Systems, vol. 15, pp. 1144-1154, October 2007.
- T. Xu and K. Chakrabarty, "Parallel scan-like test and multiple-defect
diagnosis for digital microfluidic biochips",
IEEE Transactions on Biomedical Circuits and Systems, vol. 1, pp. 148-158, June 2007.
2008
- F. Su and K. Chakrabarty,
"High-level synthesis of digital microfluidic biochips",
ACM Journal on
Emerging Technologies in Computing Systems, vol. 3, Article 16, January 2008.
- P. Y. Paik, V. K. Pamula and K. Chakrabarty,
"Adaptive cooling of integrated
circuits using digital microfluidics",
IEEE Transactions on
VLSI Systems, vol. 16, pp. 432-443, April 2008.
- Z. Wang and K. Chakrabarty, "Test-quality/cost optimization using
output-deviation-based reordering of test patterns",
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 27, pp. 352-365, February 2008.
- S. Samii, M. Selkala, E. Larsson, K. Chakrabarty and Z. Peng,
"Cycle-accurate test power modeling and its application to SoC test
architecture
design and scheduling",
IEEE Transactions on Computer-Aided Design of
Integrated Circuits and Systems, vol. 25, pp. 973-977, May 2008.
- N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A.
Virazel, S. Pravossoudovitch and C. Landrault,
"A selective scan slice encoding technique for test data volume and test power
reduction", Journal of Electronic Testing:
Theory and Applications, vol. 24, pp. 353-364, August 2008.
- Z. Wang and K. Chakrabarty,
"Test data compression using selective encoding of scan slices",
IEEE Transactions on
VLSI Systems, vol. 16, pp. 1429-1440, November 2008.
- D. Xiang, Y. Zhao, K. Chakrabarty and H. Fujiwara, "A
reconfigurable scan architecture with weighted scan-enable signals for
deterministic BIST", IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 27, pp. 999-1012, June 2008.
- T. Xu and K. Chakrabarty,
"Integrated droplet routing and defect tolerance in the synthesis of digital
microfluidic biochips",
ACM Journal on
Emerging Technologies in Computing Systems, vol. 4., no. 3, Article 11, August 2008.
- P. Y. Paik, V. K. Pamula and K. Chakrabarty, "A digital microfluidic
approach to chip cooling'', IEEE Design & Test of Computers, vol. 25, pp. 372-381, July/August 2008.
- T. Xu and K. Chakrabarty, "Defect-aware high-level synthesis
and module placement for microfluidic biochips",
IEEE Transactions on Biomedical Circuits and Systems, vol. 2, pp. 50-62, March 2008.
- A. Sehgal, S. Bahukudumbi and K. Chakrabarty,
"Power-aware SOC test planning for effective utilization of port-scalable
testers",
ACM Transactions on
Design Automation of Electronic Systems, vol. 13, no. 3, Article 53, July 2008.
- T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara,
"Thermal-aware test access mechanism optimization for system-on-chips",
IEICE Transactions on Information and Systems,
vol. E91-D, pp. 2440--2448, October 2008.
- T. Xu and K. Chakrabarty, "A droplet-manipulation method for
achieving high-throughput in cross-referencing-based digital
microfluidic
biochips", IEEE Transactions on Computer-Aided
Design of Integrated Circuits and Systems, vol. 27, pp. 1905-1917, November 2008.
2009
- S. Bahukudumbi and K. Chakrabarty, "Test-length and TAM
optimization for wafer-level reduced pin-count testing of core-based
SoCs", IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 111-120, January 2009.
- Z. Wang, H. Fang, K. Chakrabarty and M. Bienek, "Deviation-based LFSR reseeding for test-data compression",
IEEE Transactions on
Computer-Aided Design of Integrated Circuits and Systems, vol. 29, pp. 259-271, February 2009.
- S. K. Goel, E. J. Marinissen, A. Sehgal and K. Chakrabarty,
"Testing of SOCs with hierarchical cores: Common fallacies, test-access
optimization, and test scheduling", IEEE
Transactions on Computers, vol. 58, pp. 409-423, March 2009.
- S. Bahukudumbi, S. Ozev, K. Chakrabarty and V. Iyengar, "Wafer-level
defect screening for "big-D/small-A" mixed-signal SoCs",
IEEE Transactions on VLSI Systems, vol. 17, pp. 587-592, April 2009.
- S. Bahukudumbi and K. Chakrabarty, "Power management using
test-pattern ordering for wafer-level test-during-burn-in",
IEEE Transactions on VLSI Systems, vol. 17, pp. 1730-1741, December 2009.
- Y. Zhang, Q, Xu and K. Chakrabarty,
"SOC test-architecture optimization for the testing of embedded cores and
signal-integrity faults on core-external interconnects",
ACM Transactions on
Design Automation of Electronic Systems, vol. 14, Article 4, January 2009.
- X. Wu, P. Falkenstern, K. Chakrabarty and Y. Xie, "Scan-chain
design and optimization for three-dimensional integrated circuits",
ACM Journal on
Emerging Technologies in Computing Systems, vol. 5, Article 9, July 2009.
- Z. Wang, K. Chakrabarty and S. Wang, "Integrated LFSR reseeding, test-access optimization, and test scheduling for core-based system-on-chip,
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 28, pp. 1251-1264, August 2009.
- Y. Zhao and K. Chakrabarty, "On-line testing of lab-on-chip using
reconfigurable digital-microfluidic compactors",
International Journal of Parallel
Programming, vol. 37, pp. 370-388, August 2009.
- T. Xu and K. Chakrabarty, "Fault modeling and functional test methods for digital microfluidic biochips", IEEE Transactions for Biomedical Circuits and Systems, vol. 3, pp. 241-253, August 2009.
- V. Mao, V. Thusu, C. Dwyer and K. Chakrabarty, "Connecting fabrication defects to fault models and SPICE simulations for DNA self-assembled nanoelectronics", IET Computers and Digital Techniques, vol. 3, pp. 553-569, 2009.
- H.-H. S. Lee and K. Chakrabarty, ""Test challenges for 3D integrated circuits", IEEE Design & Test of Computers, vol. 26, pp. 26-35, September/October 2009.
2010
- H. Sabbineni and K. Chakrabarty, "An energy-efficient data delivery scheme for delay-sensitive traffic in wireless sensor networks", accepted for publication in International Journal of Distributed Sensor Networks, 2009.
- K. Chakrabarty, "Design automation and test solutions for digital microfluidic biochips" (invited paper), IEEE Transactions on Circuits and Systems I, vol, 57, pp. 4-17, January 2010.
- T. Xu, K. Chakrabarty and V. K. Pamula, "Defect-tolerant design and optimization of a digital microfluidic biochip for protein crystallization", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2009.
- H. Fang, K. Chakrabarty and H. Fujiwara, "RTL DFT techniques to enhance defect coverage for functional test sequences", accepted for publication in Journal of Electronic Testing: Theory and Applications, 2009.
- M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Test-pattern selection for screening small-delay defects in very-deep submicron integrated circuits", accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2010.
Refereed Conference Papers
1993-1997
- K. Chakrabarty and J. P. Hayes, "Aliasing-free error detection (ALFRED)", Proc. IEEE VLSI Test Symposium, pp. 260-267, April 1993.
- K. Chakrabarty and J. P. Hayes, "Balance testing of logic circuits", Proc. Int. Symp. Fault-Tolerant Computing, pp. 350-359, June 1993.
- K. Chakrabarty and J. P. Hayes, "DFBT: A design-for-testability technique based on balance testing", Proc. IEEE/ACM Design Automation Conference, pp. 351-357, June 1994.
- K. Chakrabarty and J. P. Hayes, "Efficient test response compression for multiple-output circuits", Proc. IEEE Int. Test Conference, pp. 501-510,
October 1994.
- K. Chakrabarty, B. T. Murray and J. P. Hayes, "Optimal
space compaction of test responses",
Proc. 1995 IEEE Int. Test Conference, pp. 834-843, October 1995.
- K. Chakrabarty, B. T. Murray, J. Liu and M. Zhu "Test width compression for
built-in self testing", Proc. 1997 IEEE International
Test Conference, pp. 328-337, November 1997.
- V. Iyengar, K. Chakrabarty and B. T. Murray, "Test set
encoding for testing sequential circuits",
Proc. 1997 IEEE Instrumentation & Measurement Technology
Conference, pp. 1442-1447, Ottawa, Canada, May 1997.
1998
- V. Iyengar, K. Chakrabarty and B. T. Murray,
"Deterministic built-in self testing of sequential circuits using
precomputed test patterns",
Proc. 1998 IEEE VLSI Test Symposium, pp. 418-423, April
1998.
- K. Chakrabarty,
"Design of optimal linear space compactors for built-in self-test",
Proc. 1998 IEEE Instrumentation &
Measurement Technology Conference, pp. 413-418, St. Paul, MN, May 1998.
1999
- K. Chakrabarty, B. T. Murray and V. Iyengar,
"Built-in pattern generation for high-performance
circuits using twisted ring counters",
1999 IEEE VLSI Test Symposium, pp. 22-27, 1999.
- P. F. Flores, H. C. Neto, K. Chakrabarty and J. P. M. Silva,
"Test pattern generation for width compression in BIST",
Proc. 1999 IEEE International Symposium on
Circuits and Systems, pp. 114-118, Orlando, FL, May 1999.
- S. R. Das, T. Barakat, E. M. Petriu, M. H. Assaf and K.
Chakrabarty, "Space compaction revisited",
Proc. 1999 IEEE Instrumentation &
Measurement Technology Conference, pp. 849-854, Venice, Italy, May 1999.
- K. Chakrabarty, "Test scheduling for core-based systems", Proc. International Conference on Computer-Aided
Design (ICCAD) , pp. 391-394, 1999.
- K. Chakrabarty and S. R. Das,
"Test set embedding for mixed-mode BIST",
Proc. 1999 IEEE Instrumentation &
Measurement Technology Conference, pp. 1778-1783, Venice, Italy, May 1999.
2000
- K. Chakrabarty, "Design of system-on-a-chip test access architectures
using integer linear
programming", Proc. 2000 IEEE VLSI Test
Symposium, pp. 127-134, 2000.
- M. Seuring and K. Chakrabarty, "Space compaction of test responses for IP cores using orthogonal
transmission functions", Proc. IEEE VLSI Test
Symposium, pp. 213-219, 2000.
- A. Chandra and K. Chakrabarty, "Test data compression for system-on-a-chip using Golomb codes", Proc. IEEE VLSI Test
Symposium, pp. 113-120, Montreal, 2000
(Received the James Beausang Memorial Best Student Paper Award)
- K. Chakrabarty and S. Swaminathan, "Built-in self testing of high-performance circuits using twisted-ring counters", Proc. 2000 IEEE International Symposium on Circuits and Systems, pp. I-72--I-76, 2000.
- K. Chakrabarty, "Design of system-on-a-chip test access architectures under
place-and-route and power constraints", Proc. IEEE/ACM Design
Automation Conference (DAC), pp. 432-437, 2000.
- S. R. Das, J. Liang, M. Sudarma, E. M. Petriu, W. B. Jone and K.
Chakrabarty, "Increasing fault coverage using a new probability measure in
output compaction based on switching theory formulation",
Proc. IASTED Conference on Modeling, Identification and Control, pp. 589-596,
Innsbruck, Austria,
February 2000.
- S. R. Das, J. Liang, E. M. Petriu, W. B. Jone and K. Chakrabarty,
"Data compression in space under generalized mergeability based on concepts
of cover table and frequency ordering", Proc. Instrumentation and
Measurement Technology Conference, pp. 217-222, Baltimore, MD, May 2000.
- H. Date, V. Iyengar, K. Chakrabarty and
M. Sugihara, "Mathematical modeling of intellectual property protection
using partially-mergeable cores",
Proc. IEEE International Conference on Parallel and Distributed Processing
Techniques and Applications, pp. 611-617, 2000.
2001
- H. Qi, S. S. Iyengar and K. Chakrabarty, "Distributed multi-resolution
data integration using mobile agents", Proc. IEEE Aerospace Conference, vol. 3, pp. 1133-1141, 2001.
- K. Chakrabarty, R. Mukherjee and A. Exnicios, "Synthesis of
transparent circuits for hierarchical and system-on-a-chip test",
Proc. IEEE International Conference on VLSI Design, pp. 431-436,
Bangalore, India, January 2001.
- V. Swaminathan and K. Chakrabarty,
"Real-time
task scheduling for energy-aware embedded systems",
IEEE Real-Time Systems Symposium (Work-In-Progress Sessions), Orlando, FL, November 2000.
- V. Swaminathan and K. Chakrabarty,
"Investigating the effect of voltage switching on low-energy task scheduling
in hard real-time systems", Proc. Asia South Pacific Design Automation Conference, pp. 251-254,
2001.
- B. B. Bhattacharya, A. Dmitriev, M. Goessel and K. Chakrabarty,
"Synthesis of single-output space compactors with application to scan-based IP cores", Proc. Asia South Pacific Design
Automation Conference, pp. 496-501, 2001.
- T. Zhang, K. Chakrabarty and R. B. Fair, "Design of reconfigurable
composite microsystems based on hardware/software co-design principles",
Proc. International Conference on Modeling and
Simulation of Microsystems, pp. 148-152, 2001.
- J. Ding, K. Chakrabarty and R. B. Fair, "Reconfigurable microfluidic
system architecture based on two-dimensional electrowetting arrays", Proc. International Conference on Modeling and
Simulation of Microsystems, pp. 181-185, 2001.
- A. Chandra and K. Chakrabarty,
"Efficient test data compression and decompression for system-on-a-chip using
internal scan chains and Golomb coding",
Proc. Design Automation and Test in Europe (DATE) Conference, pp. 145-149, 2001.
(Received Best Paper Award)
- A. Chandra, K. Chakrabarty and S. R. Das, "On
using twisted-ring counters for testing embedded cores in
system-on-a-chip designs", Proc. IEEE Instrumentation and Measurement
Technology Conference, PP. 216-220, 2001.
- S. R. Das, M. H. Assaf, E. M. Petriu,
W.-B. Jone and K. Chakrabarty, "A novel approach to designing aliasing-free
space compactors based on switching theory formulation using a new probability
measure under generalized mergeability", Proc. IEEE Instrumentation and Me
asurement
Technology Conference, pp. 198-203, May 2001.
- K. Chakrabarty, S. S. Iyengar, H. Qi and E. Cho, "Coding theory
framework for target location in distributed sensor networks", Proc. International Symposium on Information Technology: Coding and Computing, pp. 130 -134, 2001.
- A. Morosov, K. Chakrabarty, B. B. Bhattacharya and M. Goessel,
"Design of parameterizable error-propagating space compactors for
response observation", Proc. IEEE VLSI Test Symposium, pp. 48-53, 2001.
- V. Iyengar and K. Chakrabarty, "Precedence-based,
preemptive, and power-constrained test scheduling
for system-on-a-chip", Proc. IEEE VLSI Test Symposium, pp. 368-374, 2001.
- A. Chandra and K. Chakrabarty, "Frequency-directed
run-length (FDR) codes with application to
system-on-a-chip test data compression", Proc. IEEE VLSI Test Symposium, pp. 42-47, 2001.
- K. Chakrabarty and S. S. Iyengar, "Sensor placement in distributed sensor networks using a coding
theory framework", Proc. IEEE International
Symposium on Information Theory, p. 157, 2001.
- S. Swaminathan and K. Chakrabarty, "A deterministic
scan-BIST architecture with application to field testing of high-availability
systems", Proc. IEEE Custom Integrated Circuits Conference, pp. 259-262,
May 2001.
- V. Swaminathan, K. Chakrabarty and S. S. Iyengar,
"Dynamic I/O power management for hard real-time systems",
Proc. International Symposium on Hardware/Software Co-Design
(CODES), pp. 237-242, April 2001.
- A. Chandra and K. Chakrabarty, "Combining low-power scan testing
and test data compression for system-on-a-chip",
Proc. IEEE/ACM Design Automation Conference (DAC), pp. 166-169, June 2001.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen,
"Test wrapper and test acess mechanism co-optimization for system-on-a-chip",
Proc. IEEE International Test Conference, pp. 1023-1032, 2001.
- H. Qi, X. Wang, S. S. Iyengar and K. Chakrabarty, "Multisensor data fusion in distributed sensor networks using mobile agents", Proc. International Conference on Information Fusion (FUSION 2001), pp. TuC2-11--TuC2-16, 2001.
2002
- T. Zhang, K. Chakrabarty and R. B. Fair, System performance evaluation with SystemC for two PCR microelectrofluidic systems",
Proc. International
Conference on Modeling and Simulation of Microsystems, pp. 48--53, 2002.
- T. Zhang, K. Chakrabarty and R. B. Fair, "Integrated hierarchical design of
microelectrofluidic systems using SystemC",
Proc. International
Conference on Modeling and Simulation of Microsystems, pp. 144-149, 2002.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Efficient wrapper/TAM Co-optimization for large SOCs", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 491-498, 2002.
- A. Chandra and K. Chakrabarty, "Test resource partitioning and reduced pin-count testing based on test data
compression", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 598-603, 2002.
- C. Liu, K. Chakrabarty and M. Goessel, "An interval-based diagnosis scheme for identifying failing vectors in a
scan-BIST Environment", Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 382-386, 2002.
- A. Chandra, K. Chakrabarty and R. A. Medina, "How effective are compression codes for reducing test data volume?", Proc. IEEE VLSI Test Symposium, pp. 91-96, 2002.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "On using rectangle packing for SOC wrapper/TAM co-optimization", Proc. IEEE VLSI Test Symposium, pp. 253-258, 2002.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Integrated wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume
reduction for SOCs", Proc.
IEEE/ACM Design Automation Conference, pp. 685-690, 2002.
- A. Chandra and K. Chakrabarty, "Reduction of SOC test data
volume, scan power and testing time using alternating run-length codes",
Proc.
IEEE/ACM Design Automation Conference, pp. 673-678, 2002.
- V. Swaminathan and K. Chakrabarty, "Dynamic I/O power management in real-time systems",
Proc. International Conference on Information Fusion (FUSION 2002), pp. 965-972, 2002.
- V. Swaminathan and K. Chakrabarty, "Pruning-based energy-optimal device scheduling in hard real-time systems",
Proc. International Symposium on Hardware/Software Co-Design, pp. 175-180, 2002.
- S. S. Dhillon, K. Chakrabarty and S. S. Iyengar, "Sensor placement for grid coverage under imprecise detections",
Proc. International Conference on Information Fusion (FUSION 2002), pp. 1581-1587, 2002.
- V. Iyengar, S. K. Goel, E. J. Marinissen and K. Chakrabarty, "Test
resource optimization for multi-site testing of SOCs under ATE
memory depth constraints", Proc. IEEE International
Test Conference, pp. 1159-1168, 2002.
- E. J. Marinissen, V. Iyengar and K. Chakrabarty, "A set of benchmarks for modular testing
of SOCs", Proc. IEEE International
Test Conference, pp. 519-528, 2002.
- V. Iyengar, K. Chakrabarty and E. J. Marinissen, "Recent advances
in TAM optimization, test scheduling, and test resource
management for modular testing of core-based SOCs" (invited paper), Proc.
IEEE Asian
Test Symposium, pp. 320-325, 2002.
- A. Dmitriev, M. Goessel and K. Chakrabarty, "Robust space
compaction of
test responses", Proc. IEEE Asian Test
Symposium, pp. 254-259, 2002.
- V. Swaminathan, C. B. Schweizer, K. Chakrabarty and A. A. Patel,
"Experiences in implementing an energy-driven task scheduler in RT-linux",
Proc. Real-Time and Embedded Technology and
Applications Symposium, pp. 229-239, 2002.
- Y. Zou and K. Chakrabarty, "Sensor deployment and target localization for tactical surveillance", Proc. Army Science Conference, Paper ID: OP-12, 2002.
- S. S. Dhillon and K. Chakrabarty, "A fault-tolerant approach to sensor deployment in distributed sensor networks", Proc. Army Science Conference, Paper ID: JP-05, 2002.
- Y. Zhang and K. Chakrabarty, "Macromodeling of battery discharge and recovery for mobile embedded systems", Proc. Army Science Conference, Paper ID: FP-06, 2002.
2003
- Y. Zou and K. Chakrabarty, "Sensor deployment and target localization
based on virtual forces", IEEE Infocom Conference, pp. 1293-1303,
2003.
- C. Liu and K. Chakrabarty, "Compact dictionaries for fault diagnosis
in BIST", Proc. IEEE International Symposium on
Quality Electronic Design, pp. 105-110, 2003.
- D. K. Pradhan, C. Liu and K. Chakrabarty, "EBIST: A novel test generator with built-in fault detection capability", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 220-224, 2003.
- V. Iyengar, A. Chandra, S. Schweizer and K. Chakrabarty, "A unified approach
for SOC testing using test data compression and TAM optimization", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1188-1189, 2003.
- Y. Zhang and K. Chakrabarty, "Energy-aware adaptive checkpointing in embedded real-time systems", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 918-923, 2003.
- C. Liu and K. Chakrabarty, "A partition-based approach for identifying
failing scan cells in scan-BIST with applications to system-on-chip fault
diagnosis", Proc. IEEE/ACM Design, Automation and Test
in Europe (DATE) Conference, pp. 230-235, 2003.
- S. S. Dhillon and K. Chakrabarty, "Sensor placement
for effective coverage and surveillance in distributed sensor networks",
Proc. IEEE Wireless Communications and Networking Conference, pp. 1609-1614, 2003.
- Y. Zou and K. Chakrabarty, "Energy-aware target
localization in wireless sensor networks",
Proc. IEEE International Conference on Pervasive Computing and Communications, pp. 60-67, 2003.
- V. Iyengar, K. Chakrabarty, M. D. Krasniewski and G. N. Kumar, "Design and
optimization of multi-level TAM architectures for hierarchical
SOCs", Proc. IEEE VLSI Test Symposium, pp. 299-304, 2003.
- L. Li and K. Chakrabarty, "Test data compression using dictionaries with fixed-length indices", Proc. IEEE VLSI Test Symposium, pp. 219-224, 2003.
- V. K. Pamula and K. Chakrabarty, "Cooling of integrated circuits using
droplet-based microfluidics", Proc. ACM/IEEE
Great Lakes Symposium on VLSI, pp. 84-87, 2003.
- A. Sehgal, V. Iyengar, M. D. Krasniewski and K. Chakrabarty,
"Test cost reduction for SOCs using virtual TAMs and Lagrange multipliers",
Proc. IEEE/ACM Design Automation Conference, pp. 738-743, 2003.
- L. Li and K. Chakrabarty, "Deterministic BIST based on a reconfigurable interconnection network", Proc. IEEE International Test Conference, pp. 460-469, 2003.
- F. Su, S. Ozev and K. Chakrabarty, "Testing of droplet-based microelectrofluidic systems", Proc. IEEE International Test Conference, pp. 1192-1200, 2003.
- Y. Zou and K. Chakrabarty, "Uncertainty-aware sensor deployment
algorithms for surveillance applications",
Proc. Globecom 2003-Next Generation Networks and Internet, pp. 2972-2976, 2003.
- S. Kajihara, Y. Doi, L. Li and K. Chakrabarty, "On combining
pinpoint test set relaxation and run-length codes for
reducing test data volume", IEEE Int. Conf.
Computer Design (ICCD), pp. 387-392, 2003.
- L. D. Oliver, K. Chakrabarty and R. R. Brooks, "Locomotion-based
dynamic power management in embedded real-time systems",
Proceedings of SPIE
Volume: 5205,
Advanced Signal Processing Algorithms, Architectures, and Implementations XIII,
pp. 185-196, 2003.
- A. Sehgal, S. Ozev and K. Chakrabarty, "TAM optimization for mixed-signal SOCs using test wrappers for analog cores", Proc. IEEE International Conference on CAD, pp. 95-99, 2003.
- V. Swaminathan and K. Chakrabarty, "Generalized network flow techniques for dynamic voltage scaling in hard real-time systems", Proc. IEEE International Conference on CAD, pp. 21-25, 2003.
- Y. Zhang, K. Chakrabarty and V. Swaminathan, "Energy-aware fault
tolerance in fixed-priority real-time embedded systems", Proc. IEEE International Conference on CAD, pp. 209-213, 2003.
- Y. Zhang and K. Chakrabarty,
"Fault recovery based on checkpointing for hard real-time embedded
systems", Proc. IEEE Int. Symp. Defect and Fault
Tolerance in VLSI Systems, pp. 320-327, 2003.
2004
- Y. Zhang and K. Chakrabarty, "Task feasibility analysis and dynamic voltage scaling in fault-tolerant
real-time embedded systems", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1170-1175, 2004.
- A. Sehgal and K. Chakrabarty, "Efficient modular testing of SOCs
using dual-speed TAM architectures", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 422-427, 2004.
- M. Tehranipour, M. Nourani and K. Chakrabarty, "Nine-coded compression technique with application to reduced pin-count testing
and flexible on-chip decompression", Proc. IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, pp. 1284-1289, 2004.
- C. Liu, K. Dwarakanath, K. Chakrabarty and R. D. Blanton, "Compact dictionaries for diagnosis of unmodeled faults in scan-BIST", Proc. IEEE Int. Symposium on VLSI, pp. 173-178, 2004.
- P. Y. Paik, V. K. Pamula and K. Chakrabarty, "Thermal effects on
droplet transport in digital microfluidics with
applications to chip cooling",
Proc. International Conference on Thermal, Mechanics and
Thermomechanical Phenomena in Electronic Systems (iTherm), pp. 649-654, 2004.
- Y. Zhang, R. P. Dick and K. Chakrabarty, "Energy-aware deterministic
fault tolerance in distributed real-time embedded
systems", Proc. IEEE/ACM Design Automation
Conference, pp. 550-555, 2004.
- F. Su, S. Ozev and K. Chakrabarty, "Test planning and test resource
optimization for droplet-based microfluidic
systems", Proc. European Test Symposium,
pp. 72-77, 2004.
- F. Su, S. Ozev and K. Chakrabarty, "Concurrent testing of
droplet-based microfluidic systems for
multiplexed biomedical assays", Proc. International
Test Conference, pp. 883-892, 2004.
- A. Sehgal, S. K. Goel, E. J. Marinissen and K. Chakrabarty,
"IEEE P1500-compliant test wrapper design for hierarchical cores",
Proc. International Test Conference, pp. 1203-1212, 2004.
- F. Su and K. Chakrabarty, "Architectural-level synthesis of digital
microfluidics-based biochips", Proc. IEEE
International Conference on CAD, pp. 223-228, 2004.
2005
- K. Chakrabarty, "Design, testing, and applications of digital microfluidics-based biochips"
(embedded tutorial), Proc. IEEE International Conference on
VLSI Design, pp. 221-226, 2005.
- L. Li, K. Chakrabarty, S. Kajihara and S. Swaminathan, "Efficient space/time compression
to reduce test data volume and testing time for IP cores",
Proc. IEEE International Conference on VLSI Design, pp. 53-58, 2005.
- Y. Doi, S. Kajihara, X. Wen,
L. Li and K. Chakrabarty, "Test compression for scan circuits
using scan polarity adjustment and pinpoint test relaxation", IEEE/ACM Asia South Pacific Design Automation Conference, pp. 59-64, 2005.
- A. Sehgal, F. Liu, S. Ozev and K. Chakrabarty, "Test planning for
mixed-signal SoCs with wrapped analog cores",
Proc. Design, Automation and Test in Europe (DATE) Conference, pp. 137-142, 2005.
- L. Li and K. Chakrabarty, "Hybrid BIST based on repeating sequences
and cluster analysis",
Proc. Design, Automation and Test in Europe (DATE)
Conference, pp. 1142-1147, 2005.
- F. Su and K. Chakrabarty, "Design of fault-tolerant and
dynamically-reconfigurable microfluidic biochips",
Proc. Design, Automation and Test in Europe
(DATE) Conference, pp. 1202-1207, 2005.
- F. Su, K. Chakrabarty and V. K. Pamula, "Yield enhancement of
digital microfluidics-based biochips using space
redundancy and local reconfiguration",
Proc. Design, Automation and Test in Europe
(DATE) Conference, pp. 1196-1201, 2005.
- P. Rosinger, B. Al-Hashimi and K. Chakrabarty, "Rapid generation of
thermal-safe test schedules",
Proc. Design, Automation and Test in Europe
(DATE) Conference, pp. 840-845, 2005.
- F. Su and K. Chakrabarty, "Defect tolerance for gracefully-degradable microfluidics-based biochips", Proc. IEEE VLSI Test Symposium, pp. 321-326, 2005.
- F. Su and K. Chakrabarty, "Reconfiguration techniques for
digital microfluidic biochips",
Proc. IEEE Design, Test, Integration and Packaging of MEMS/MOEMS Symposiuum, pp. 143-148, 2005.
- K. Chakrabarty and F. Su, "Design Automation Challenges for Microfluidics-based biochips''
(invited paper for special session),
Proc. IEEE Design, Test, Integration and Packaging of MEMS/MOEMS Symposium,
pp. 260-265, 2005.
- Z. Wang and K. Chakrabarty, "Built-in self-test of molecular
electronics-based nanofabrics",
Proc. IEEE European Test Symposium, 2005.
- Q. Xu, N. Nicolici and K. Chakrabarty, "Multi-frequency
wrapper design and optimization for embedded cores under average power
constraints", Proc. IEEE/ACM Design Automation
Conference, pp. 123-128, 2005.
- F. Su and K. Chakrabarty, "Unified high-level synthesis and module
placement for defect-tolerant
microfluidic biochips",
Proc. IEEE/ACM Design Automation Conference, pp. 825-830, 2005.
- Y. Zou and K. Chakrabarty, "Fault-tolerant self-organization in
sensor networks", Proc. International
Conference on Distributed Computing in Sensor Systems, Published in Lecture Notes in Computer Science LCNS 3560, pp. 191-205, Springer, 2005.
- Z. Wang and K. Chakrabarty, "Test data compression for IP
embedded cores using selective encoding of scan slices", Proc. IEEE International Test Conference, pp. 581-590, 2005.
- Z. Wang and K. Chakrabarty, "Using built-in self-test and
adaptive recovery for defect tolerance in molecular electronics-based
nanofabrics", Proc. IEEE International Test
Conference, pp. 477-486, 2005.
- F. Su, W. Hwang, A. Mukherjee and K. Chakrabarty, "Defect-oriented
testing and diagnosis of digital microfluidics-based biochips",
Proc. IEEE International Test Conference, pp. 487-496, 2005.
- P. Y. Paik, V. K. Pamula, M. G. Pollack and K. Chakrabarty, "Coplanar
digital microfluidics using standard printed circuit board processes",
Proc. International Conference on Miniaturized Chemical
and Biochemical Analysis Systems (MicroTAS), 2005.
- K. Chakrabarty and F. Su, "System-level design automation tools for
digital microfluidic biochips", Proc. IEEE International
Conference on Hardware-Software Codesign and System Synthesis (invited paper in special session), pp. 201-206, 2005.
- A. Sehgal, S. Ozev and K. Chakrabarty, "A flexible design methodology
for analog test wrappers in mixed-signal SOCs",
Proc. IEEE International
Conference on Computer Design, pp. 137-142, 2005.
(Received Best Paper Award)
- E. Tafaj, P. Rosinger, B. M. Al-Hashimi and K. Chakrabarty, "Improving
thermal-safe test scheduling for core-based systems-on-chip using shift
frequency scaling", Proc. Defect and Tolerance in VLSI Systems Symposium, pp. 544-551, 2005.
- A. Sehgal and K. Chakrabarty, "Test planning for the effective
utilization of port-scalable testers for heterogeneous core-based SOCs",
Proc. IEEE International
Conference on Computer-Aided Design, pp. 88-93, 2005.
- K. Chakrabarty, "Synthesis and reconfiguration techniques for digital
microfluidics-based biochips" (keynote paper), Proc.
International Conference & Exhibition on Micro Electro, Opto, Mechanical
Systems and
Components (MICRO SYSTEM Technologies), pp. 24-39, 2005.
- P. Y. Paik, V. K. Pamula and K. Chakrabarty "Heat transfer
analysis for adaptive hot-spot cooling of integrated circuits using
digital
microfluidics", Proc. ASME Int.
Mechanical Engineering Congress and Symp., 2005.
2006
- A. Sehgal, S. K. Goel, E. J. Marinissen and K. Chakrabarty,
"Hierarchy-aware and area-efficient test infrastructure design for core-based
system
chips", Proc. Design, Automation and Test in
Europe (DATE) Conference, pp. 285-290, 2006.
- F. Su, W. Hwang and K. Chakrabarty, "Droplet routing in the
synthesis of digital microfluidic biochips",
Proc. Design, Automation and Test in
Europe (DATE) Conference, pp. 323-328, 2006.
- Z. Wang, K. Chakrabarty and M. Goessel, "Test set enrichment
using a probabilistic fault model and the theory of output deviations",
Proc. Design, Automation and Test in
Europe (DATE) Conference, pp. 1275-1280, 2006.
- T. Zhou and K. Chakrabarty, "Authentication of sensor
network flooding based on neighborhood cooperation", Proc. IEEE Wireless Communications and Networking Conference,
2006.
- L. D. Oliver, K. Chakrabarty and H. Z. Massoud, "An evaluation of
the impact of gate oxide tunneling on
dual-Vt-based leakage reduction techniques",
Proc. ACM/IEEE GLSVLSI, pp. 105-110, 2006.
- W. Hwang, F. Su and K. Chakrabarty, "Automated design of pin-constrained digital microfluidic arrays for
lab-on-a-chip applications", Proc. IEEE/ACM Design Automation Conference, pp. 925-930, 2006.
- S. Samii, E. Larsson, K. Chakrabarty and Z. Peng, "Cycle-accurate test power modeling and its application to SOC test scheduling",
Proc. IEEE International Test Conference, Paper 32.1, 2006.
- S. Bahukudumbi and K. Chakrabarty, "Defect-oriented and time-constrained wafer-level test length selection for core-based SOCs",
Proc. IEEE International Test Conference, Paper 19.1, 2006.
- Z. Wang and K. Chakrabarty, "An efficient test pattern
selection
method for improving defect coverage with reduced test data volume and test
application time",
Proc. IEEE Asian Test Symposium, pp. 333-338, 2006.
- N. Badereddine, Z. Wang, P. Girard, K. Chakrabarty, A. Virazel,
S. Pravossoudovitch and C. Landrault,
"Power-aware test data compression for embedded IP cores",
Proc. IEEE Asian Test Symposium, pp. 5-10, 2006.
- D. Xiang, Y. Zhao, K. Chakrabarty, J. Sun and H. Fujiwara,
"Compressing test data for deterministic BIST using a reconfigurable
scan
architecture",
Proc. IEEE Asian Test Symposium, pp. 299-304, 2006.
- T. Xu and K. Chakrabarty,
"Droplet-trace-based array partitioning and a pin assignment algorithm for the
automated design of digital microfluidic biochips",
Proc. IEEE/ACM International Conference on Hardware/Software
Codesign and System Synthesis, pp. 112-117, 2006.
- K. Chakrabarty,
"Automated design of microfluidics-based biochips: connecting biochemistry to
electronics CAD",
Proc. IEEE International Conference on Computer Design (invited paper), pp. 93-100, 2006.
2007
- T. Xu, K. Chakrabarty and F. Su,
"Defect-aware synthesis of droplet-based microfluidic biochips",
Proc. IEEE International Conference on VLSI Design, pp. 647-652, 2007.
(Received Best Paper Award)
- S. Bahukudumbi and K. Chakrabarty,
"Test-length selection, reduced pin-count testing,
and TAM optimization for wafer-level testing of core-based digital SoCs",
IEEE International Conference on VLSI
Design, pp. 459-464, 2007.
- A. Kumar, K. Chakrabarty and C. Rama Mohan,
"An ECO technique for removing crosstalk violations in
clock networks",
Proc. IEEE International Conference on VLSI Design, pp. 283-288, 2007.
- S. Bahukudumbi, S. Ozev, K. Chakrabarty and V. Iyengar, "A wafer-level defect screening technique to reduce test and packaging
costs for "big-D/small-A" mixed-signal SoCs",
Proc. IEEE/ACM Asia South Pacific Design Automation Conference, pp. 823-828, 2007.
- Z. Wang, K. Chakrabarty and S. Wang, "SoC testing using LFSR
reseeding, and scan-slice-based TAM optimization
and test scheduling", Proc. Design, Automation and Test in
Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364591, pp. 201-206, 2007.
- T. Xu and K. Chakrabarty, "A cross-referencing-based droplet manipulation
method for high-throughput and pin-constrained digital microfluidic arrays",
Proc. Design, Automation and Test in
Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364651, pp. 552-557, 2007.
- I. O'Connor, B. Courtois, K. Chakrabarty, N. Delorme, M. Hampton,
J. Hartung, "Heterogeneous systems on chip and systems in package",
Proc. Design, Automation and Test in
Europe (DATE) Conference, DOI: 10.1109/DATE.2007.364683, pp. 737-742, 2007.
- T. Xu and K. Chakrabarty, "Parallel scan-like testing and fault
diagnosis techniques for
digital microfluidic biochips",
Proc. IEEE European Test Symposium, pp. 63-68, 2007.
- Z. Wang, K. Chakrabarty and M. Bienek, "A seed-selection method
to increase defect coverage for
LFSR-reseeding-based test compression",
Proc. IEEE European Test Symposium, pp. 125-130, 2007.
- Q. Xu, Y. Zhang and K. Chakrabarty, "SOC test architecture optimization
for signal integrity
faults on core-external
interconnects",
Proc. IEEE/ACM Design Automation Conference, pp. 676-681, 2007.
- T. Xu and K. Chakrabarty, "Integrated droplet routing in the synthesis
of microfluidic biochips",
Proc. IEEE/ACM Design Automation Conference, pp. 948-953, 2007.
- K. Chakrabarty, "Digital microfluidics: connecting biochemistry to electronic system design" (invited keynote paper),
Proc. ASME International Conference on Nanochannels, Microchannels and
Minichannels, 2007.
- T. Zhou, R. Roy Choudhury, P. Ning and K. Chakrabarty, "Privacy-preserving
detection of Sybil attacks in vehicular networks",
Proc. Annual International Conference on Mobile and
Ubiquitous
Systems: Computing, Networking and Services
(MOBIQUITOUS 2007), 2007, DOI: 10.1109/MOBIQ.2007.445101.
- T. Xu and K. Chakrabarty, "Functional testing of digital
microfluidic biochips", Proc. IEEE
International
Test Conference, 2007.
- Q. Xu, Y. Zhang and K. Chakrabarty, "Test-wrapper designs for the
detection of signal-integrity faults on core-external interconnects of SoCs",
Proc. IEEE International Test Conference,
2007.
- T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara,
"Thermal-safe test access mechanism and wrapper co-optimization for
system-on-chip",
Proc. IEEE Asian Test Conference, pp. 187-192, 2007.
- D. Xiang, K. Chakrabarty, D. Hu and H. Fujiwara,
"Scan testing for path delay faults with reduced test data volume, test
application
time, and hardware cost",
Proc. IEEE Asian Test Conference, pp. 329-334, 2007.
2008
- S. Bahukudumbi, K. Chakrabarty and R. Kacprowicz, "Test scheduling
for
wafer-level test-during-burn-in of core-based SoCs", Proc. IEEE Design, Automation and Test in Europe (DATE) Conference, pp. 1103-1106, 2008.
- A. Larsson, E. Larsson, K. Chakrabarty, P. Eles and Z. Peng,
"Test-architecture optimization and test scheduling for SOCs with core-level
expansion of compressed test patterns", Proc. IEEE
Design, Automation and Test in Europe (DATE) Conference, pp. 188-193, 2008.
- M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Test-pattern grading
and pattern selection for
small-delay defects", IEEE VLSI Test
Symposium, pp. 233-239, 2008.
- S. Bahukudumbi and K. Chakrabarty, "Test-pattern ordering for wafer-level
test-during-burn-in",
IEEE VLSI Test
Symposium, pp. 193-198, 2008.
- T. Xu and K. Chakrabarty, "Automated design of digital
microfluidic lab-on-chip under pin-count constraints", Proc. ACM International Symposium on Physical Design, pp. 90-98, 2008 (Invited Paper).
- T. Xu and K. Chakrabarty, "Broadcast electrode-addressing for
pin-constrained multi-functional digital microfluidic biochips",
Proc.
IEEE/ACM Design Automation Conference, pp. 173-178, 2008.
- Y. Zhao and K. Chakrabarty, "On-line testing of lab-on-chip
using digital microfluidic compactors", Proc.
IEEE International On-line Testing Symposium, pp. 213-218, 2008.
- Y. Zhao, T. Xu and K. Chakrabarty, "Built-in self-test and fault diagnosis for lab-on-chip using digital
microfluidic logic gates", Proc. IEEE
International
Test Conference, 2008
(Selected as "Top-10 Paper", and listed in the 2009 conference proceedings).
- M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "Interconnect-aware and
layout-oriented test-pattern selection for
small-delay defects", Proc. IEEE
International
Test Conference, 2008.
- V. Mao, C. Dwyer and K. Chakrabarty, "Fabrication defects and fault models for DNA self-assembled nanoelectronics", Proc. IEEE
International
Test Conference, 2008 (Selected as "Top-10 Paper", and listed in the 2009 conference proceedings).
- T. Xu, K. Chakrabarty and V. K. Pamula, "Design and optimization of a digital microfluidic biochip for protein crystallization",
Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 297-301, 2008.
- S. Bahukudumbi and K. Chakrabarty, "Power management for wafer-level
test during burn-in", IEEE Asian Test
Symposium, pp. 231-236, 2008.
- A. Larsson, X. Zhang, E. Larsson and K. Chakrabarty,
"Core-level compression technique selection and SOC test architecture design",
IEEE Asian Test Symposium, pp. 277-282, 2008.
- D. Mitra, S. Ghoshal, H. Rahaman, B. B.
Bhattacharya, D. Dutta Majumder and K. Chakrabarty,
"Accelerated functional testing of digital microfluidic biochips",
IEEE Asian Test Symposium, pp. 295-300, 2008.
- Y. Zhang, K. Chakrabarty and T. Xu, "Digital microfluidic
logic gates", Proc. 3rd International Conference on Nano-Networks, 2008.
- X. Wu, Y. Chen, K. Chakrabarty and Y. Xie, "Test-access mechanism optimization for core-based three-dimensional SOCs", Proc. IEEE International Conference on Computer Design, pp. 212-218, 2008.
- K. Chakrabarty, "Towards fault-tolerant digital microfluidic
lab-on-chip: defects, fault modeling, testing, and reconfiguration", Proc.
IEEE International Conference on Biomedical Circuits and Systems (invited paper), pp. 329-332, 2008.
- T. Xu, V. K. Pamula and K. Chakrabarty,
"Automated, accurate and inexpensive
solution-preparation on a digital microfluidic biochip", Proc.
IEEE International Conference on Biomedical Circuits and Systems, pp. 301-304, 2008.
2009
- T. E. Yu, T. Yoneda, K. Chakrabarty and H. Fujiwara,
"Thermal-aware TAM design and test scheduling with cycle-accurate
power profiles, test partitioning and bandwidth matching",
Proc.
IEEE Asia South Pacific Design Automation Conference, pp. 793-798, 2009.
- Y. Zhao and K. Chakrabarty, "Cross-contamination avoidance for droplet routing in digital
microfluidic biochips", Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1290-1295, 2009.
- M. Yilmaz and K. Chakrabarty, "Seed selection in LFSR-reseeding-based test compression for the
detection of small-delay defects",
Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1488-1493, 2009.
- X. Kavousianos and K. Chakrabarty, "Generation of compact test sets with high defect coverage",
Proc. IEEE/ACM Design, Automation and Test in Europe Conference, pp. 1130-1135, 2009.
- T. Xu and K. Chakrabarty, "Design-for-testability for digital microfluidic biochips", Proc. IEEE VLSI Test Symposium, pp. 309-314, 2009.
- H. Fang, K. Chakrabarty, A. Jas, S. Patil and C. Trimurti, "RT-level deviation-based grading of functional test sequences", Proc. IEEE VLSI Test Symposium, pp. 264-269, 2009.
- L. D. Oliver, K. Chakrabarty and H. Z. Massoud, "Dual-threshold pass-transistor logic design",
Proc. ACM Great Lakes Symposium on VLSI (GLSVLSI), pp. 291-296, 2009.
- T. Xu and K. Chakrabarty, "Towards design-for-testability
for digital microfluidics", Proc. Symposium
on Design, Test, Integration, and Packaging of MEMS/MOEMS (DTIP), pp. 329-333, 2009.
- Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, ``Physical defect modeling for fault insertion in system reliability test", Proc. International Test Conference, 2009.
- H. Fang, K. Chakrabarty and R. Parekhji, "Bit-operation-based seed augmentation for LFSR reseeding with high defect coverage", Proc. IEEE Asian Test Symposium, pp. 331-335, 2009.
- D. Xiang, B. Yin and K. Chakrabarty, "Compact test generation for small-delay defects using testable-path information", Proc. IEEE Asian Test Symposium, pp. 424-429, 2009.
- B. Noia, K. Chakrabarty and Y. Xie, "Test-wrapper optimization for embedded cores in TSV-based three-dimensional SOCs", Proc. IEEE International Conference on Computer Design, 2009.
- L. Jiang, Q. Xu, K. Chakrabarty and T. M. Mak, "Layout-driven test-architecture design and optimization for 3D SoCs under pre-bond test-pin-count constraint", Proc. IEEE International Conference on Computer-Aided Design, pp. 191-196, 2009.
- Y. Zhao, R. Sturmer, K. Chakrabarty and V.K. Pamula, "Optimization of droplet routing for an n-plex bioassay on a digital microfluidic lab-on-chip", Proc. IEEE International Conference on Biomedical Circuits and Systems, 2009.
2010
- Y. Zhao, R. Sturmer, K. Chakrabarty and V. K. Pamula, "Synchronization of concurrently-implemented fluidic operations in pin-constrained digital microfluidic biochips", IEEE International Conference on VLSI Design, 2010.
(Received Best Paper Award)
- K. Chakrabarty, "Digital microfluidic biochips: A vision for functional diversity and more than Moore", invited embedded tutorial at IEEE International Conference on VLSI Design, 2010.
- K. Peng, M. Yilmaz, M. Tehranipoor and K. Chakrabarty, "High-quality pattern selection for screening small-delay defects considering process variations and crosstalk", accepted for publication in IEEE/ACM Design, Automation
and Test in Europe (DATE) Conference, 2010.
- R. A. Shafik, B. M. Al-Hashimi and K. Chakrabarty, "Soft error-aware
design optimization of low-power and time-constrained embedded systems",
accepted for publication in
IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, 2010.
- S. Balatsouka, V. Tanentes, X. Kavousianos and K. Chakrabarty,
"Defect aware X-filling for low-power scan testing", accepted for publication in
IEEE/ACM Design, Automation and Test in Europe (DATE) Conference, 2010.
- Y. Zhao and K. Chakrabarty, "Pin-count-aware online testing of digital
microfluidic biochips", accepted for publication in IEEE VLSI Test
Symposium, 2010.
- Z. Zhang, Z. Wang, X. Gu and K. Chakrabarty, "Board-level fault diagnosis
using Bayesian inference", accepted for publication in IEEE VLSI Test Symposium, 2010.
- K. Peng, J. Thibodeau, M. Yilmaz, K. Chakrabarty and M. Tehranipoor, "A
novel hybrid method for SDD pattern grading and selection", accepted for
publication in IEEE VLSI Test Symposium, 2010.