Hello,
  
It seems like flattening a cell creates one more discrepancy when I run $
This is what I'm trying to do: 
 
I am creating a 2:1 mux. I put the inverter and the two passgates that m$
2:1 mux next to each other in layout such that the VDD and ground are to$
At this point, I hadn't flattened the cells. I then ran LVS check..... i$
me there are 2 discrepancies namely: VDD and ground ports are missing, w$
fine. But when I flattened all the cells and ran LVS again, it gave me 1 
discrepancy even though I didn't "make" VDD and ground ports. Here is wh$
said in the Calibre - LVS  RVE window:

Answer,
 When you flattend your layout, the VDD and ground
ports of our base inverter and pass gate cells
now became top cell Vdd and ground, hence your errors
went away. In fact other signal ports of these base cells 
now become top cell ports. Hence, perhaps this is
the cause of your missing port N that is in your layout
and not schematics(source). 
 
 
Also, you cannot undo the flatten command unless you 
go back to a previous layout version using IC. 

jim

====================================================================



Prof. Morizio,
 
I want to make a new project window other than the one we are using for lab
assignment. But I don't know how to inport those layouts, schemetic and symbols
that we created to the new project window. And I don't know how to make the
project files not public but can be seen by group members either?
 
Gary Pan

ANSWER:
You can copy an existing library in ICStudio by using a simple mouse copy
and rename this to a new library. To open this up use the chmod -R 777 directory
name command.

========================================================================

Prof. Morizio,
 
My team mate (Astha Vijay) and I discussed the possibility of creating
something
like a shared linux account that both of us can access. The reason is that each
of us will be working on different portions of the project but we'll merge
everything together at the end. Currently with each person having a different
account, I don't know if its possible for us to swap icstudio files. Thanks for
looking into this.
 
ANSWER:
 You really do not need a shared linux account to create a VLSI
project with multiple users. All you have to do is open your project
files up with public read permissions and have your partners be 
able to read them. The project team leader
should be able to read symbols for schematics and add cell layouts 
into the top cell of the project.

Note your mgc_location_map file should include all project team members
soft reference files. ex: 
$MYLAY, $MYNETS, $JMORIZIONETS, $JMORIZIOLAY, 
with the appropriate search paths.