ECE 261 Project Information
A design project is an important part of this course.
You will work in groups of four students to specify, design,
verify, and do a layout of an application-oriented system. The functionality
of the design (making it work) is more important than maximum operating speed
or the number of transistors. All projects will take advantage of hierarchy of
subsystems so that these subsystems can be first implemented
and completed for partial credit. Thus, you will have at a minimum,
complete subsystems, rather than an incomplete top-level system if time
becomes a problem. Your group should discuss your project with the TA and
me to check its magnitude and scope. Here is a list of previous projects
1) (Fault-Tolerant) 16-bit Carry-Lookahead Adder
2) Digital Noise Removal
3) Booth-Encoded Radix-4 16-bit Multiplier
4) Implementation of Clarion 8-Channel Cochlear Implant
5) Voting Machine on a Chip
6) Data-Dependent Instruction Queue Decision and Insertion
7) Visitation Quantifier for Rocky Peaks Theme Park
8) 8-bit MIPS Processor
Each team must identify its leader and organize itself as a
design unit reporting to the instructor. The leader's responsibilities
and task assignments are to be worked out in consultation with the
course instructor. The teams and the project scope should be multidisciplinary, i.e., each team should include students with interests
from several of the following areas: analog, digital, computer science,
computer engineering, signal processing, BME, electronics, photonics,
etc. You are therefore strongly encouraged to team up with students from other
departments.You are also encouraged to form teams that include graduate and
undergraduate students. Projects that do not satisfy this teaming requirement will not be approved.
Each team must submit a
proposal describing with sufficient clarity the design project and
how the team will satisfy the following requirement: students must be prepared for engineering
practice through the curriculum culminating in a major design experience
based on the knowledge and skills acquired in earlier course work, and
incorporating ENGINEERING STANDARDS and REALISTIC CONSTRAINTS that
include MOST of the following considerations: Economic; Environmental;
Sustainability; Manufacturability; Ethical; Health and Safety; Social;
There will be several checkpoints during the semester to verify the progress
of the design. For each checkpoint, write up a small report describing the
project and giving the state of the design and verification. The report
should be expanded as progress is made. The final report should discuss 1)
the function of the system, 2) system-level architecture, 3) subsystem design,
4) schematic and cell designs, 5) meaningful simulation results, 6)
proposed testing methodologies, and 7) lessons learned, problems faced, and
You should form your project teams by September 29. Hand in your project
proposal in class on September 29. You are required to present your project
ideas in class on October 6.
1) The first checkpoint is to verify that you have a good idea of
what you will design, and have some idea of how you will design and
test it. You are required to prepare a high-level, behavioral specification
for your design. You can use C/C++, Matlab, VHDL, Verilog or any other
behavioral specification method that can be simulated. (A specification in
English is not acceptable!)
Simulate your design and make sure that it
works. Also, try to estimate the sizes of various components of your
design (eg. number of gates or transistors).
Deadline: October 12 (reports due in class).
2) The second checkpoint is to verify
that the design has progressed to a more detailed level. You must
implement the schematics of your blocks and hook them up properly.
You will need to run Qsim on all your blocks.
Deadline: October 26 (reports due in class).
3) The third checkpoint is to verify that you have completed the layout of
all your blocks and started routing and placement.
Deadline: November 21 (reports due in class).
4) The final checkpoint is when the project is due. The
entire layout should be complete and verified. All verification tools must
have been run (DRC and LVS). The report should be complete and the design
should be ready to be sent for fabrication. Note that
checkpoints 3 and 4 are usually not easy. Sometimes cells do not
fit together in the proposed floorplan, routine is very complex, or
module interfaces are incompatible.
Each group will give oral
presentations on the project during the last week of the semester.