ECE 261: CMOS VLSI Design Methodologies, Fall 2009
Lab 3
Assigned: October 29, Due: November 12, at 1:15 PM

The purpose of this lab is to become more familiar with the simulation tools Eldo and become more productive with the Mentor IC Station and DA/IC tools. You will gain further practice in running the simulation tools and in designing hierarchically. In addition, you will get some hands-on experience with basic ratioed logic design.

You are required to design and simulate a logic function that implements F= ABC + DE. First, design a ratioless version, and then implement a ratioed pseudo-nMOS version. (You can use a ratioless inverter.) In the latter case, you will have to determine an appropriate size for the pMOS load. While minimum device areas for the layout are not necessary, you are required to do your schematics and layouts hierarchically.