ECE 261: CMOS VLSI Design Methodologies, Fall 2009
Lab 2
Assigned: October 10, Due: October 22, 3:45 PM.

In Lab 1, you designed a simple combinational circuit and became familiar with the Mentor Graphics schematic editor, layout editor, and the DRC and LVS tools. The purpose of this lab assignment is to design a simple CMOS sequential circuit and become familiar with hierarchy and simulation tools: Modelsim for logic simulation, and ELDO for more detailed, analog simulation.

Design a master-slave D flip-flop using transmission gates. First, design transmission gates and inverters, and create symbols for them. Then instantiate these modules and use them in the flip-flop design. Once your design passes DRC and LVS, verify it for functional correctness using Modelsim. You are then required to simulate using ELDO. This will allow you to determine the maximum speed at which you can run your clock. The TA will help you in setting up your Modelsim and ELDO files.

You are required to show your design to the TA and demonstrate that it passes DRC and LVS. You are also required to demonstrate your Modelsim and ELDO simulation results.