5.8.2 SPICE2 or PSpice JFET Model Parameters

The SPICE dc model^32,33 uses a further simplification of the expression for I_Dsat given in Eq. (5.125). First, V_T=V_bi-V_p from Eq. (5.106) is used to eliminate V_bi in Eq. (5.125):

$$I_{D_{sat}}=\frac{G_oV_p}{3}\left[ 1-\frac{3(V_p+V_T-V_{GS})}{V_p}+2\left(\frac{ V_p+V_T-V_{GS}}{V_p}\right)^{3/2}\right].$$ (5.128)

The $2(\ldots)^{3/2}$ term may be written as 2[1-(V_GS-V_T)/V_p]^3/2 and expanded in a three term binomial series to give

$$2\left[1-\left(\frac{V_{GS}-V_T}{V_p}\right)\right]^{3/2}=2\... ...1}{2}\frac{1}{2}\left( \frac{V_{GS}-V_T}{V_p}\right)^2\right].$$ (5.129)

Equation (5.128) now becomes

$$\frac{G_oV_p}{3}\left[1-3+3\left(\frac{V_{GS}-V_T}{V_p}\right) +2-3\left(\frac{V_{GS}-V_T}{V_p}\right) \right .$$ I_Dsat =

$$\left . +\frac{3}{4}\left(\frac{V_{GS}-V_T}{V_p}\right)^2\right] .$$ (5.130)

Cancellation of common terms gives

$$I_{D_{sat}}=\frac{G_o}{4V_p}(V_{GS}-V_T)^2.$$ (5.131)

Previously G_o was given in Eq. (5.113) as $q\mu_n n(W/L)a$, and V_p was given in Eq. (5.104) as $qna^2/2\epsilon_{Si}$. Then,

$$\frac{G_o}{4V_p}=\frac{q\mu_n n}{4}\frac{W}{L}a\frac{2\epsilon_{Si}}{qna^2}= \frac{\mu_n}{2a}\frac{W}{L}\epsilon_{Si},$$ (5.132)

or

$$\fbox{$\beta \equiv {\displaystyle {\mu_n \over\displaystyle 2a}} {\displaystyle W\over\displaystyle L}\epsilon_{Si} $ } ~.$$ (5.133)

Equations (5.131) and (5.133) may be combined to give

$$\fbox{$I_{D_{sat}} = \beta(V_{GS}-V_T)^2$ } ~.$$ (5.134)

Equation (5.134) is a commonly used approximation for the JFET.

In the saturation region, the depletion region near the drain will increase as V_DS exceeds V_Dsat. This maximum in the depletion depth [see Fig. 5.28 (b)] will move toward the source and effectively shortens the channel length L much like the Early voltage effects in bipolar junction transistors. This effect is called channel length modulation and is represented by the parameter $\lambda$. The SPICE representation becomes

$$I_{D_{sat}} = \beta (V_{GS}-V_T)^2(1+\lambda V_{DS}),$$ (5.135)

where $\lambda$ is related to the output conductance given by

$$g_d \equiv \left . \frac{\partial I_D}{\partial V_{DS}}\right\vert _{V_{DS}}.$$ (5.136)

Table 5.3. SPICE2 or PSpice JFET Model Parameters
	Text	SPICE		Default
No.	Symbol	Keyword	Parameter Name	Value	Units
1	VT	VTO	threshold voltage	-2	V
2	$\beta$	BETA	transconductance parameter	10-4	A/V2
3	$\lambda$	LAMBDA	channel-length modulation	0	V-1
4	RD	RD	drain ohmic resistance	0	$\Omega$
5	RS	RS	source ohmic resistance	0	$\Omega$
hline 6	CGS	CGS	zero-bias gate-source capacitance	0	F
7	CGD	CGD	zero-bias gate-drain capacitance	0	F
8	Vbi	PB	gate built-in potential	1	V
9	Is	IS	gate saturation current	10-14	A
10	FC	FC	coefficient for forward-bias depletion capacitance	0.5
11	kf	KF	flicker-noise coefficient	0
12	$\alpha_f$	AF	flicker-noise exponent	1

The SPICE2 or PSpice parameters for the JFET are given in Table 5.3 and have been described by Massobrio and Antognetti.³³ The optional parameters (PAR1, PAR2,$\cdots$) are represented by the SPICE2 Keywords. For example, if no value is given for the threshold voltage, the default value of -2 V will be used. It should be noted that V_T, as given by Eq. (5.107), is related to the pinchoff voltage V_p which depends on the carrier concentration and thickness a of the conducting layer. The next parameter is BETA which was given in Eq. (5.133) and contains the gate width W and length L. LAMBDA, the channel-length modulation parameter, was introduced in Eq. (5.135).

The source and drain resistances, RS and RD, represent the IR drop between the source and drain contacts and the conducting channel. These resistances cause the experimentally measured g_m to be less than the actual channel transconductance.³⁴ The gate-source capacitance and gate-drain capacitances, CGS and CGD, are either experimentally determined or estimated as described in Ref. 35. The built-in potential PB for the p-n junction gate was given in Eq. (4.60) and the p-n junction gate saturation current IS is the diffusion saturation current given in Eqs. (4.115) and (4.116). The coefficient for forward-bias depletion capacitance FC is the same as for the p-n junction SPICE parameters in Table 5.1. The noise parameters are also the same as for the p-n junction in Table 5.1. In circuit applications, the manufacturer would be expected to provide $V_T,~\beta$, and I_S for a particular fabrication process. The SPICE large-signal model equivalent circuit for the n-channel JFET is shown in Fig. 5.32.

 

Figure 5.32: SPICE2 large-signal model equivalent circuit for the n-channel JFET ( Ref. 35).

The two diodes represented in the equivalent circuit by I_GS and I_DS are given by³⁶

$$I_{GS}=I_S[\exp(qV_{GS}/kT)-1],$$ (5.137)

and

$$I_{DS}=I_S[\exp(qV_{DS}/kT)-1].$$ (5.138)

A small conductance, GMIN=10^-12 mho, is connected in parallel with I_GS and I_DS as V_GSGMIN and V_DSGMIN to aid in convergence. The capacitances C_GS and C_GD are represented by³⁵

$$C_{GS}=C_{GS}(0)(1-V_{GS}/V_{bi})^{-m}~{\rm for}~V_{GS}<{\tt FC}\times V_{bi},$$ (5.139)

and

$$C_{GS}=[C_{GS}(0)]/{\tt F}_2({\tt F}_3+mV_{GS}/V_{bi})~{\rm for}~V_{GS}\geq {\tt FC}\times V_{vi}.$$ (5.140)

The parameters F₂ and F₃ are given as³⁵

$${\tt F}_2=(1-{\tt FC})^{1+m},$$ (5.141)

and

$${\tt F}_3=1-{\tt FC}(1+m).$$ (5.142)

In SPICE2 or PSpice, the grading parameter m is 0.5 and cannot be varied.