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Date
|
Lab
|
Lectures
|
Readings
|
Assignments
Due
|
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8/26
|
No Lab
|
1. (PDF)
Introduction, switching-networks, AND/OR/NOT
|
Preface, Chapter 1, begin Chapter 2
|
|
|
8/28
|
2. (PDF)
Boolean algebra, synthesis, NAND/NOR, full adder
|
Finish Chapter 2
|
|
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9/2
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Lab 0
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3. (PDF)
Combinational circuits, XOR/XNOR, logic synthesis, CAD
|
Ch.
3 (pp. 73-93)
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Assignment
1 due
All assignments (throughout the semester) are due at start of
lecture
Late penalty is
~100% (exceptions may apply)
|
|
9/4
|
4. (PDF)
Continue synthesis and CAD, basic VHDL
|
Ch.
3 (pp. 94-113)
|
|
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9/9
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Lab 1
|
5. (PDF)
Review MOSFETs, NMOS/PMOS, CMOS, PLDs, PALs, CPLDs, comparators
|
Ch.
3 (pp. 114-134)
|
Assignment
2 due
|
|
9/11
|
6. (PDF)
FPGAs, fan-in / fan-out, buffers, transmission
gates, tri-state gates
|
Ch.
3 (pp. 134-145)
|
New date: Assignment
2 due
|
|
9/16
|
(w/
pre-lab)
Lab 2
FPGA/CPLD
programming
tutorial
Sample Quartus project file
|
7. (PDF)
K-maps: SOP, POS, X; function minimization
|
Ch.
4 (pp. 164-202)
|
Assignment
3 due
|
|
9/18
|
8. (PDF)
Optimization algorithms, multiple outputs
|
Ch.
4 (pp. 203-228)
|
|
|
9/23
|
Lab 3
|
9. (PDF)
Factoring, Quine-McCluskey, more VHDL
|
Ch.
5 (pp. 246-256)
|
Assignment
4 due
|
|
9/25
|
10. (PDF) Number
systems, bin/ octal/ hex
|
Ch.
5 (pp. 256-278)
|
|
|
9/30*
|
(Continue Lab 3
if needed)
|
11. (PDF) Sign
magnitude, 1's & 2's complement, negative numbers
|
Ch.
5 (pp. 278-309)
|
Assignment
5 due
|
|
10/2
|
Exam I
No class notes, no calculators, no book, 1 page of exam
notes (8.5"x11")
|
|
10/7
|
(w/
pre-lab)
Lab 4
|
Finish lecture 11.
|
|
10/9
|
12. (PDF)
9/10's complement, memory, and latches
|
Ch.
6 (pp. 316-339)
|
|
|
10/14
|
Lab 5
|
13. (PDF)
More latches, flip-flops, MUX logic (again)
|
Ch.
6 (pp. 339-363)
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Assignment
6 due
|
|
10/16
|
14. (PDF)
Parity, fast adders, fixed-point, floating point, ranges, ASCII, intro to
FSMs
|
|
|
|
10/21
|
(new lab 5.5 starting S'10)
|
15. (PDF)
Counters, finite state machines
|
Ch.
7 (pp. 380-398)
|
Reprieve!
|
|
10/23
|
16. (PDF)
Registers, counters, more FSMs, state
minimization, FSM analysis, more VHDL
|
Finish
Ch.
7
|
|
|
10/28*
|
Lab 6
|
17. (PDF)
More FSMs, comb. wrap-up,
memories.
|
Ch. 8
|
Assignment
7 due
|
|
10/30
|
18.
(PDF)
More FSMs, protocomputer
introduction, RTL ALU, control design
|
|
|
|
11/4
|
Lab 7
Project Proposals due in lab
|
19. (PDF)
Protocomputer continued...
|
|
Assignment
8 due
|
|
11/6
|
Exam II
No class notes, no calculators, no book, 2 pages of exam
notes (8.5"x11")
|
|
11/11
|
Continue
Lab 7
Project
simulations
due by end of this
week (except M/T)
(>80% functional)
|
20. (PDF)
More protocomputer parts, optimizations,
JSR/RET, compilers
|
|
Assignment
9 due
|
|
11/13
|
21. (PDF)
Turing machines, asynchronous design, hazard avoidance,
flow tables, stable states, races
|
|
|
|
11/18
|
Continue
Lab 7
|
22. (PDF)
Asynchronous design examples
|
|
|
|
11/20
|
23. (PDF) Encodings: Gray, Reed-Solomon, RAIDs,
parity, Hamming, error correcting codes
|
|
|
|
11/25
|
No lab, except M/T
|
No class
|
|
|
|
11/27
|
No class
|
|
|
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12/2
|
Project demos
|
24. (PDF) Testing
logic circuits
|
Ch. 9
|
|
|
12/4
|
25. (PDF)
Path analysis, built-in-self-test, signature generation.
|
|
Assignment
10 due
(Reference and
example
parts)
Protocomputer VHDL template
and a sample main_memory.mif file
(start with
this, defer to its specifications)
|
|
Final Exam: Dec. 8, 7-10pm in 203 Teer. (3 sheets OK) (The Registrar establishes this date and time)
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