Duke University
ECE 52, Introduction to Digital Systems
                   (and Machine Organization)
Fall 2011


Instructor:
Prof. Chris Dwyer
Lecture
: T/Th., 10:05a-11:0a, 125 Hudson Hall
Labs: M-Th, See schedule of courses

Office Hours: ~9-10am M-F, Twinnie's Cafe, OR, by appointment.

Text: Brown and Vranesic, "Fundamentals of Digital Logic with VHDL Design", 2nd or 3rd ed.

 

Syllabus

 
Nota bene: All materials presented during lecture, used in lab, or assigned for homework 
                are copyrighted (even if not explicitly marked)
and owned by either 
                Duke University, your textbook publisher, or other parties.

                The following lecture PDFs can change at any moment. These slides are here 
                to help save you time during lectures (not to replace lecture). You
                are expected to attend lecture and take your own notes.
               (The username and password for access will be given in class)

Unless otherwise noted, no exercise solutions (from the current or previous semesters)
may be shared prior to the assignment due date. (This policy includes the contents of digital files.)

Collaboration on homework exercises is encouraged but must not devolve into the sharing of problem solutions.

You are required to uphold the Duke Community Standard at all times.

 

Date

Lab

Lectures

Readings

Assignments Due

8/30

Do the following on your own:


1. Install:
Quartus II Web Edition, 9.1 Service Pack 2


2. Complete:
A DE2 VHDL Tutorial


3. Read:
the
ECE52 DE2  guide

1. (PDF) Review: Introduction, switching-networks, AND/OR/NOT

Preface, Chapter 1, begin Chapter 2

 

9/1

2. (PDF) Review: Boolean algebra, synthesis, NAND/NOR, full adder

Finish Chapter 2

 

9/6

Lab 0

3. (PDF) Combinational circuits, XOR/XNOR, logic synthesis, CAD

Ch. 3 (pp. 73-93)

Review lectures
1 and 2

9/8

4. (PDF) Continue synthesis and CAD, basic VHDL

Ch. 3 (pp. 94-113)

 Assignment 1 due


All assignments are due at the start of lecture.

 

-10% per day awarded for late work

9/13

Lab 1

5. (PDF) Review MOSFETs, NMOS/PMOS, CMOS.
Lab 2 prep: comparators

Ch. 3 (pp. 114-134)


9/15

6. (PDF) FPGAs, fan-in / fan-out, buffers, transmission gates, tri-state gates

Ch. 3 (pp. 134-145)

Assignment 2 due

9/20

 

(w/ pre-lab)

Lab 2

7. (PDF) K-maps: SOP, POS; function minimization (part-1)

Ch. 4 (pp. 164-185)


9/22*

8. (PDF) BCD adder, incomplete functional specs., Number systems, bin/ octal/ hex

Ch. 5 (pp. 249-258)

 Assignment 3 due

9/27

 

Lab 3

9. (PDF) More arithmetic circuits, shifting, negative numbers, sign magnitude

Ch. 5 (pp. 259-266)


9/29

10. (PDF)  1's and 2's complement, memory, and latches

Ch. 5 (pp. 267-272)

 Assignment 4 due

10/4

M/T/W Lab sections only:

(w/ pre-lab)

Lab 4

Exam I 

No class notes, no calculators, no book, 1 page of exam notes (8.5"x11")

10/6


11. (PDF) More latches, flip-flops, intermediate VHDL

Ch. 7 (pp. 381-401)


10/11

Thursday Lab section only:

(w/ pre-lab)

Lab 4


NO CLASS



10/13

12. (PDF)  Registers, RTL, bus operations, and intro. to the Protocomputer

Ch. 7 (pp. 404-418)

Assignment 5 due

10/18

(Continue Lab 4)

13. (PDF) Protocomputer parts, program execution



10/20

14. (PDF)  Subroutines, protocomputer optimizations, compilation


 

 DUE TO LAB TA by end of week:


Protocomputer components check


See Assignment 6

Turn-in waveforms for all major components (registers, ALU, excluding the controller)
(by end of week)

10/25

15. (PDF) Parity, fast adders, fixed-point, floating point, number ranges


 

Ch 5. (pp. 273-279, 295-299)



(continue with Assignment 6)

10/27

16. (PDF) Optimization algorithms (part-2), multi-level synthesis, and multiple outputs



Ch. 4 (pp. 186-219)



(continue with Assignment 6)

11/1

(Continue Lab 5)

17. (PDF) Factoring, Quine-McCluskey

Ch. 4 (pp. 186-219)

(continue with Assignment 6)

11/3

18. (PDFASCII, counters,
finite state machines

 

Ch. 7 (pp. 404-415

"Big" Assignment 6 due  (by Sunday!)

Send a ZIP archive of the entire project folder to your lab TA.


(See also: Reference and example parts)

 

Start with this: Protocomputer VHDL template

11/8

Lab 6

19. (PDF) More counters, more FSMs, state minimization

 Ch. 8  (pp. 479-500)

 


11/10

Exam II


No class notes, no calculators, no book, 2 pages of exam notes (8.5"x11")

11/15

"Big"
Lab 7

20. (PDF) State reduction, combinational wrap-up.

Ch. 8 (513-551)

 Assignment 7 due

11/17

21. (PDF) FSM analysis,  advanced VHDL

Finish Ch. 8


11/22

No labs meet this week

(Continue Lab 7)

22. (PDF) Turing machines, asynchronous design, hazard avoidance, flow tables, stable states, races

Ch. 9 (pp. 577-603)

Assignment 8 due

11/24


NO CLASS



11/29

(Continue Lab 7)

23. (PDF) Asynchronous design examples

 Finish Ch. 9



12/1

24. (PDF) Encodings: Gray, Reed-Solomon, RAIDs, parity, Hamming, error correcting codes

 

Assignment 9 due

12/6

Project demos

and

Individual lab exams

25. (PDF) Testing logic circuits

Ch. 11

 

12/8

26. (PDF) Path analysis, built-in-self-test, signature generation.

 


Final Exam: Friday Dec. 16, 2-5pm in 125 Hudson Hall. (3 sheets of exam notes are OK)

 
 

Some useful extrania:

Lab Notes from lecture

IC Datasheets

DE2 programming tutorial

Alternate DE2 pin table (very useful!)

Espresso files: format and options
      You can use espresso in at least two ways:

    1. Use SSH and your ECE login credentials at login.ece.duke.edu
    The espresso program file can be found at /opt/local/bin/espresso
     on login.ece.duke.edu. (it should already be in your path)

OR

    2. Download this WinXP port (by D. W. Hart) of the original espresso program from the SIS/OCTtools.

Arbitrary length binary-to-BCD-converter (PDF)

Linear feedback shift register (LFSR) taps for (pseudo) random number generation

ECE 52 Protocomputer Assembler